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Re: [PATCH 00/25] AMD GCN Port
- From: Bernd Edlinger <bernd dot edlinger at hotmail dot de>
- To: "ams at codesourcery dot com" <ams at codesourcery dot com>
- Cc: GCC Patches <gcc-patches at gcc dot gnu dot org>
- Date: Mon, 17 Sep 2018 10:51:22 +0000
- Subject: Re: [PATCH 00/25] AMD GCN Port
<ams@codesourcery.com> writes:
> Given a pattern with a number of operands:
>
> (match_operand 0 "" "=&v")
> (match_operand 1 "" " v0")
> (match_operand 2 "" " v0")
> (match_operand 3 "" " v0")
>
> GCC will currently increment "reject" once, for operand 0, and then decrement
> it once for each of the other operands, ending with reject == -2 and an
> assertion failure. If there's a conflict then it might try to decrement reject
> yet again.
>
> Incidentally, what these patterns are trying to achieve is an allocation in
> which operand 0 may match one of the other operands, but may not partially
> overlap any of them. Ideally there'd be a better way to do this.
I have seen something similar in the arm.md:
where this allocation problem is solved differently:
(define_insn_and_split "*arm_subdi3"
[(set (match_operand:DI 0 "arm_general_register_operand" "=&r,&r,&r")
(minus:DI (match_operand:DI 1 "arm_general_register_operand" "0,r,0")
(match_operand:DI 2 "arm_general_register_operand" "r,0,0")))
DI registers are always consecutive register pairs,
but they should not partially overlap.
They solve that by using alternatives.
Bernd.