This is the mail archive of the gcc-patches@gcc.gnu.org mailing list for the GCC project.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

Re: [GCC][PATCH v2][Aarch64] Exploiting BFXIL when OR-ing two AND-operations with appropriate bitmasks




On 08/28/2018 11:53 PM, James Greenhalgh wrote:
On Wed, Aug 01, 2018 at 10:07:23AM -0500, Sam Tebbs wrote:
+   ones from the MSB.  */
+bool
+aarch64_is_left_consecutive (HOST_WIDE_INT i)
+{
+  return (i | (i - 1)) == HOST_WIDE_INT_M1;
exact_log2(-i) != HOST_WIDE_INT_M1?

I could change this but I'm not sure what benefit it would have over the original implementation. You're welcome to explain so as I could be missing something.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]