This is the mail archive of the
mailing list for the GCC project.
Re: [GCC][PATCH v2][Aarch64] Exploiting BFXIL when OR-ing two AND-operations with appropriate bitmasks
- From: Kyrill Tkachov <kyrylo dot tkachov at foss dot arm dot com>
- To: Sam Tebbs <sam dot tebbs at arm dot com>, James Greenhalgh <James dot Greenhalgh at arm dot com>, "gcc-patches at gcc dot gnu dot org" <gcc-patches at gcc dot gnu dot org>
- Cc: Marcus Shawcroft <Marcus dot Shawcroft at arm dot com>, Richard Earnshaw <Richard dot Earnshaw at arm dot com>, nd <nd at arm dot com>
- Date: Fri, 31 Aug 2018 11:59:08 +0100
- Subject: Re: [GCC][PATCH v2][Aarch64] Exploiting BFXIL when OR-ing two AND-operations with appropriate bitmasks
- References: <email@example.com> <20180828225320.GE22590@arm.com> <firstname.lastname@example.org>
On 30/08/18 16:53, Sam Tebbs wrote:
On 08/28/2018 11:53 PM, James Greenhalgh wrote:
> Hm, I'm not very sure about the naming here; "left consecutive" isn't a
> common phrase to denote the mask you're looking for (exact_log2 (-i) != -1
> if I'm reading right), and is misleading 0x0000ffff is 'left consecutive'
> too, just with zeroes rather than ones.
I think you're right about it not being the best naming. Do you have any
suggestions for a better name?
Naming things is hard... :(
How about aarch64_hi_bits_all_ones_p ?
>> diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h
>> index af5db9c595385f7586692258f750b6aceb3ed9c8..01d9e1bd634572fcfa60208ba4dc541805af5ccd 100644
>> --- a/gcc/config/aarch64/aarch64-protos.h
>> +++ b/gcc/config/aarch64/aarch64-protos.h
>> @@ -574,4 +574,6 @@ rtl_opt_pass *make_pass_fma_steering (gcc::context *ctxt);
>> poly_uint64 aarch64_regmode_natural_size (machine_mode);
>> +bool aarch64_is_left_consecutive (HOST_WIDE_INT);
>> #endif /* GCC_AARCH64_PROTOS_H */
>> diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
>> index fa01475aa9ee579b6a3b2526295b622157120660..3cfa51b15af3e241672f1383cf881c12a44494a5 100644
>> --- a/gcc/config/aarch64/aarch64.c
>> +++ b/gcc/config/aarch64/aarch64.c
>> @@ -1454,6 +1454,14 @@ aarch64_hard_regno_caller_save_mode (unsigned regno, unsigned,
>> return SImode;
>> +/* Implement IS_LEFT_CONSECUTIVE. Check if I's bits are consecutive
> What is IS_LEFT_CONSECUTIVE - I don't see it elsewhere in the GCC code, so
> what does the comment refer to implementing?
Thanks for pointing out this mistake, it should read
"AARCH64_IS_LEFT_CONSECUTIVE" to refer to the function definition in
aarch64-protos.h. This will of course change once a better name is