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Re: [PING 5][PATCH] [v4][aarch64] Avoid tag collisions for loads falkor


On Mon, Aug 20, 2018 at 05:39:52AM -0500, Siddhesh Poyarekar wrote:
> Ping!
> 
> On 07/24/2018 12:37 PM, Siddhesh Poyarekar wrote:
> > Hi,
> > 
> > This is a rewrite of the tag collision avoidance patch that Kugan had
> > written as a machine reorg pass back in February.
> > 
> > The falkor hardware prefetching system uses a combination of the
> > source, destination and offset to decide which prefetcher unit to
> > train with the load.  This is great when loads in a loop are
> > sequential but sub-optimal if there are unrelated loads in a loop that
> > tag to the same prefetcher unit.
> > 
> > This pass attempts to rename the desination register of such colliding
> > loads using routines available in regrename.c so that their tags do
> > not collide.  This shows some performance gains with mcf and xalancbmk
> > (~5% each) and will be tweaked further.  The pass is placed near the
> > fag end of the pass list so that subsequent passes don't inadvertantly
> > end up undoing the renames.
> > 
> > A full gcc bootstrap and testsuite ran successfully on aarch64, i.e. it
> > did not introduce any new regressions.  I also did a make-check with
> > -mcpu=falkor to ensure that there were no regressions.  The couple of
> > regressions I found were target-specific and were related to scheduling
> > and cost differences and are not correctness issues.
> > 
> > Changes from v3:
> > - Avoid renaming argument/return registers and registers that have a
> >    specific architectural meaning, i.e. stack pointer, frame pointer,
> >    etc.  Try renaming their aliases instead.
> > 
> > Changes from v2:
> > - Ignore SVE instead of asserting that falkor does not support sve
> > 
> > Changes from v1:
> > 
> > - Fixed up issues pointed out by Kyrill
> > - Avoid renaming R0/V0 since they could be return values
> > - Fixed minor formatting issues.

Sorry that this took me so long to get to.

The code is outstanding quality, a textbook example of writing an
analysis/optimization pass using modern GCC frameworks and data structures!
If you ever find the opportunity, I bet you could create some useful newcomer
training materials from this source.

This is almost OK for trunk, please just clean up the (very few) issues
detected by check_GNU_style.py and make the obvious rebase on trunk.
As I know you will ask, you can also backport to GCC 8 if you are happy with
that risk for the Falkor subtarget.

Thanks,
James

> > 
> > 2018-07-02  Siddhesh Poyarekar  <siddhesh@sourceware.org>
> > 	    Kugan Vivekanandarajah  <kugan.vivekanandarajah@linaro.org>
> > 
> > 	* config/aarch64/falkor-tag-collision-avoidance.c: New file.
> > 	* config.gcc (extra_objs): Build it.
> > 	* config/aarch64/t-aarch64 (falkor-tag-collision-avoidance.o):
> > 	Likewise.
> > 	* config/aarch64/aarch64-passes.def
> > 	(pass_tag_collision_avoidance): New pass.
> > 	* config/aarch64/aarch64.c (qdf24xx_tunings): Add
> > 	AARCH64_EXTRA_TUNE_RENAME_LOAD_REGS to tuning_flags.
> > 	(aarch64_classify_address): Remove static qualifier.
> > 	(aarch64_address_info, aarch64_address_type): Move to...
> > 	* config/aarch64/aarch64-protos.h: ... here.
> > 	(make_pass_tag_collision_avoidance): New function.
> > 	* config/aarch64/aarch64-tuning-flags.def (rename_load_regs):
> > 	New tuning flag.
> > 
> > CC: james.greenhalgh@arm.com
> > CC: kyrylo.tkachov@foss.arm.com
> > ---
> >   gcc/config.gcc                                |   2 +-
> >   gcc/config/aarch64/aarch64-passes.def         |   1 +
> >   gcc/config/aarch64/aarch64-protos.h           |  49 +
> >   gcc/config/aarch64/aarch64-tuning-flags.def   |   2 +
> >   gcc/config/aarch64/aarch64.c                  |  48 +-
> >   .../aarch64/falkor-tag-collision-avoidance.c  | 881 ++++++++++++++++++
> >   gcc/config/aarch64/t-aarch64                  |   9 +
> >   7 files changed, 946 insertions(+), 46 deletions(-)
> >   create mode 100644 gcc/config/aarch64/falkor-tag-collision-avoidance.c
> > 


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