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Re: [PATCH], Improve PowerPC switch behavior on medium code model system

On Fri, Aug 10, 2018 at 11:04:50AM -0500, Segher Boessenkool wrote:
> On Tue, Jul 31, 2018 at 10:39:21AM -0400, Michael Meissner wrote:
> > This patch adds an insn to load a LABEL_REF into a GPR.  This is needed so the
> > FWPROP1 pass can convert the load the of the label address from the TOC to a
> > direct load to a GPR.
> I don't see why you need a separate RTL insn for this.  It seems to me
> that some more generic pattern should accept label_refs.

I'm not aware of any.

> > While working on the patch, I discovered that the LWA instruction did not
> > support indexed loads.  This was due to it using the 'Y' constraint, which
> > accepts DS-form offsettable addresses, but not X-form indexed addresses.  I
> > added the Z constraint so that the indexed form is accepted.
> This part is fine.  Please split it out to a separate patch.

I just added PR target/87033 for this, and I will submit the patch shortly.

> > 	* config/rs6000/ (extendsi<mode>2): Allow reg+reg indexed
> > 	addressing.
> This should say it is changing the constraints.
> > 	(labelref): New insn to optimize loading a label address into
> > 	registers on a medium code system.
> (*labelref) btw.


Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email:, phone: +1 (978) 899-4797

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