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Re: [PATCH], Improve PowerPC switch behavior on medium code model system

On Tue, Jul 31, 2018 at 10:39:21AM -0400, Michael Meissner wrote:
> This patch adds an insn to load a LABEL_REF into a GPR.  This is needed so the
> FWPROP1 pass can convert the load the of the label address from the TOC to a
> direct load to a GPR.

I don't see why you need a separate RTL insn for this.  It seems to me
that some more generic pattern should accept label_refs.

> While working on the patch, I discovered that the LWA instruction did not
> support indexed loads.  This was due to it using the 'Y' constraint, which
> accepts DS-form offsettable addresses, but not X-form indexed addresses.  I
> added the Z constraint so that the indexed form is accepted.

This part is fine.  Please split it out to a separate patch.

> 	* config/rs6000/ (extendsi<mode>2): Allow reg+reg indexed
> 	addressing.

This should say it is changing the constraints.

> 	(labelref): New insn to optimize loading a label address into
> 	registers on a medium code system.

(*labelref) btw.


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