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Re: [PATCH], Improve PowerPC switch behavior on medium code model system
- From: Segher Boessenkool <segher at kernel dot crashing dot org>
- To: Michael Meissner <meissner at linux dot ibm dot com>, GCC Patches <gcc-patches at gcc dot gnu dot org>, David Edelsohn <dje dot gcc at gmail dot com>, Bill Schmidt <wschmidt at linux dot vnet dot ibm dot com>
- Date: Fri, 10 Aug 2018 11:04:50 -0500
- Subject: Re: [PATCH], Improve PowerPC switch behavior on medium code model system
- References: <20180731143921.GA24287@ibm-toto.the-meissners.org>
On Tue, Jul 31, 2018 at 10:39:21AM -0400, Michael Meissner wrote:
> This patch adds an insn to load a LABEL_REF into a GPR. This is needed so the
> FWPROP1 pass can convert the load the of the label address from the TOC to a
> direct load to a GPR.
I don't see why you need a separate RTL insn for this. It seems to me
that some more generic pattern should accept label_refs.
> While working on the patch, I discovered that the LWA instruction did not
> support indexed loads. This was due to it using the 'Y' constraint, which
> accepts DS-form offsettable addresses, but not X-form indexed addresses. I
> added the Z constraint so that the indexed form is accepted.
This part is fine. Please split it out to a separate patch.
> * config/rs6000/rs6000.md (extendsi<mode>2): Allow reg+reg indexed
This should say it is changing the constraints.
> (labelref): New insn to optimize loading a label address into
> registers on a medium code system.