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[PATCH][GCC][AARCH64] Use STLUR for atomic_store


Use the STLUR instruction introduced in Armv8.4-a.
This insruction has the store-release semantic like STLR but can take a
9-bit unscaled signed immediate offset.

Example test case:
```
void
foo ()
{
    int32_t *atomic_vals = calloc (4, sizeof (int32_t));
    atomic_store_explicit (atomic_vals + 1, 2, memory_order_release);
}
```

Before patch generates
```
foo:
	stp	x29, x30, [sp, -16]!
	mov	x1, 4
	mov	x0, x1
	mov	x29, sp
	bl	calloc
	mov	w1, 2
	add	x0, x0, 4
	stlr	w1, [x0]
	ldp	x29, x30, [sp], 16
	ret
```

After patch generates
```
foo:
	stp	x29, x30, [sp, -16]!
	mov	x1, 4
	mov	x0, x1
	mov	x29, sp
	bl	calloc
	mov	w1, 2
	stlur	w1, [x0, 4]
	ldp	x29, x30, [sp], 16
	ret
```

Full bootstrap and regression test done on aarch64.

Ok for trunk?

gcc/
2018-07-26  Matthew Malcomson  <matthew.malcomson@arm.com>

        * config/aarch64/aarch64-protos.h
        (aarch64_offset_9bit_signed_unscaled_p): New declaration.
        * config/aarch64/aarch64.c
        (aarch64_offset_9bit_signed_unscaled_p): Rename from
        offset_9bit_signed_unscaled_p.
        * config/aarch64/aarch64.h (TARGET_ARMV8_4): Add feature macro.
        * config/aarch64/atomics.md (atomic_store<mode>): Allow offset
        and use stlur.
        * config/aarch64/constraints.md (Ust): New constraint.
        * config/aarch64/predicates.md.
        (aarch64_sync_or_stlur_memory_operand): New predicate.

gcc/testsuite/
2018-07-26  Matthew Malcomson  <matthew.malcomson@arm.com>

	* gcc.target/aarch64/atomic-store.c: New.

Attachment: use-stlur-instruction.patch
Description: Text document


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