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[GCC][PATCH][Aarch64] Stop redundant zero-extension after UMOV when in DI mode
- From: Sam Tebbs <sam dot tebbs at arm dot com>
- To: "gcc-patches at gcc dot gnu dot org" <gcc-patches at gcc dot gnu dot org>, Marcus Shawcroft <marcus dot shawcroft at arm dot com>
- Cc: nd <nd at arm dot com>, Richard Earnshaw <richard dot earnshaw at arm dot com>, James Greenhalgh <james dot greenhalgh at arm dot com>
- Date: Mon, 23 Jul 2018 11:39:07 +0100
- Subject: [GCC][PATCH][Aarch64] Stop redundant zero-extension after UMOV when in DI mode
Hi all,
This patch extends the aarch64_get_lane_zero_extendsi instruction
definition to
also cover DI mode. This prevents a redundant AND instruction from being
generated due to the pattern failing to be matched.
Example:
typedef char v16qi __attribute__ ((vector_size (16)));
unsigned long long
foo (v16qi a)
{
return a[0];
}
Previously generated:
foo:
umov w0, v0.b[0]
and x0, x0, 255
ret
And now generates:
foo:
umov w0, v0.b[0]
ret
Bootstrapped on aarch64-none-linux-gnu and tested on aarch64-none-elf
with no
regressions.
gcc/
2018-07-23 Sam Tebbs <sam.tebbs@arm.com>
* config/aarch64/aarch64-simd.md
(*aarch64_get_lane_zero_extendsi<mode>):
Rename to...
(*aarch64_get_lane_zero_extend<mode><VDQQH:mode>): ... This.
Use GPI iterator instead of SI mode.
gcc/testsuite
2018-07-23 Sam Tebbs <sam.tebbs@arm.com>
* gcc.target/aarch64/extract_zero_extend.c: New file
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index 89e38e6..15fb661 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -3032,15 +3032,16 @@
[(set_attr "type" "neon_to_gp<q>")]
)
-(define_insn "*aarch64_get_lane_zero_extendsi<mode>"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (zero_extend:SI
+(define_insn "*aarch64_get_lane_zero_extend<mode><VDQQH:mode>"
+ [(set (match_operand:GPI 0 "register_operand" "=r")
+ (zero_extend:GPI
(vec_select:<VEL>
(match_operand:VDQQH 1 "register_operand" "w")
(parallel [(match_operand:SI 2 "immediate_operand" "i")]))))]
"TARGET_SIMD"
{
- operands[2] = aarch64_endian_lane_rtx (<MODE>mode, INTVAL (operands[2]));
+ operands[2] = aarch64_endian_lane_rtx (<VDQQH:MODE>mode,
+ INTVAL (operands[2]));
return "umov\\t%w0, %1.<Vetype>[%2]";
}
[(set_attr "type" "neon_to_gp<q>")]
diff --git a/gcc/testsuite/gcc.target/aarch64/extract_zero_extend.c b/gcc/testsuite/gcc.target/aarch64/extract_zero_extend.c
new file mode 100644
index 0000000..40d307a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/extract_zero_extend.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O3" } */
+
+typedef char v16qi __attribute__ ((vector_size (16)));
+
+unsigned long long
+foo (v16qi a)
+{
+ /* { dg-final { scan-assembler "umov\\t" } } */
+ /* { dg-final { scan-assembler-not "and\\t" } } */
+ return a[0];
+}
+