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Re: [PATCH 11/11] Increase MAX_MAX_OPERANDS limit
- From: Jakub Jelinek <jakub at redhat dot com>
- To: Dimitar Dimitrov <dimitar at dinux dot eu>
- Cc: Jeff Law <law at redhat dot com>, gcc-patches at gcc dot gnu dot org
- Date: Sat, 23 Jun 2018 20:35:23 +0200
- Subject: Re: [PATCH 11/11] Increase MAX_MAX_OPERANDS limit
- References: <20180613185805.7833-1-dimitar@dinux.eu> <b5740cbb-cf16-75ab-49a4-ac87fdfdd947@redhat.com> <20180622174155.GW7166@tucnak> <6053874.PKi0MiDhFJ@tpdeb>
- Reply-to: Jakub Jelinek <jakub at redhat dot com>
On Sat, Jun 23, 2018 at 03:26:50PM +0300, Dimitar Dimitrov wrote:
> I took arm/ldmstm.md as an inspiration. See attached machine description for
> PRU that requires the increase. I omitted this machine-generated MD file from
> my first patch set, but per comments will include it in v2.
>
> PRU has a total of 32 32-bit registers with flexible subregister addressing.
> The PRU GCC port represents the register file as 128 individual 8-bit
> registers. Rationale: http://gcc.gnu.org/ml/gcc/2017-01/msg00217.html
>
> Load/store instructions can load anywhere between 1 and 124 consecutive 8-bit
> registers. The load/store-multiple patterns seem to require const_int_operand
> offsets for each loaded register, hence the explosion of operands.
If it is consecutive only, then you could represent those that load a lot of
registers using wider modes, so represent e.g. that 124 register load as
15 DImode loads + 1 SImode.
Jakub