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[PATCH, rs6000] Change word selector to prefered location for vec_insert builtin


GCC Maintainers:

The following patch changes the word selected when extracting the word
from the second vector to insert into the first vector by the
vec_insert() builtin.  

Specifically, the test case

vector float                                                                    
fn2 (float a, vector float b)                                                   
{                                                                               
  return vec_insert (a, b, 1);                                                  
}   

without the patch  generates the code sequence 

     xscvdpspn vs0,vs1
     xxextractuw vs0,vs0,4            
     xxinsertw vs34,vs0,8

The xscvdpspn places the extracted word into words 0 and 1 of the
destination.  The xxextractuw extracts word 1 (offset of 4 bytes)from
the source.  The patch changes the offset so that the xxexractuw will
extract word 0 (offset 0 bytes) instead of word 1.  The values are the
same so there is no functional change. But it was decided that using
word 0 was preferred choice.

                 Carl Love

-----------------------------------------------------

gcc/ChangeLog:

2018-06-19  Carl Love  <cel@us.ibm.com>

	* config/rs6000/vsx.md: Change word selector to prefered location.

Signed-off-by: Carl Love <cel@us.ibm.com>
---
 gcc/config/rs6000/vsx.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index a528ef2e8..6e7a4277f 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -3934,7 +3934,7 @@
 
   operands[5] = gen_rtx_REG (V4SFmode, tmp_regno);
   operands[6] = gen_rtx_REG (V4SImode, tmp_regno);
-  operands[7] = GEN_INT (BYTES_BIG_ENDIAN ? 1 : 2);
+  operands[7] = GEN_INT (BYTES_BIG_ENDIAN ? 0 : 3);
   operands[8] = gen_rtx_REG (V4SImode, reg_or_subregno (operands[0]));
 }
   [(set_attr "type" "vecperm")
-- 
2.17.1


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