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Re: [PATCH], PowerPC long double transistion, patch #4
- From: Segher Boessenkool <segher at kernel dot crashing dot org>
- To: Michael Meissner <meissner at linux dot ibm dot com>, GCC Patches <gcc-patches at gcc dot gnu dot org>, David Edelsohn <dje dot gcc at gmail dot com>, Bill Schmidt <wschmidt at linux dot vnet dot ibm dot com>
- Date: Fri, 15 Jun 2018 13:39:49 -0500
- Subject: Re: [PATCH], PowerPC long double transistion, patch #4
- References: <20180613211015.GA3737@ibm-toto.the-meissners.org> <20180613212533.GC5861@ibm-toto.the-meissners.org>
On Wed, Jun 13, 2018 at 05:25:33PM -0400, Michael Meissner wrote:
> This patch fixes the power8 implementation of copysign for IEEE 128-bit
> floating point. In particular, the way the temporary register was allocated
> did not use the normal GCC conventions of using a clobber with match_scratch.
> Because the constraint did not include a '&', the temporary register could have
> used one of the input registers.
> --- gcc/config/rs6000/rs6000.md (revision 261512)
> +++ gcc/config/rs6000/rs6000.md (working copy)
> @@ -14102,11 +14102,8 @@ (define_expand "copysign<mode>3"
> emit_insn (gen_copysign<mode>3_hard (operands[0], operands[1],
> operands[2]));
> else
> - {
> - rtx tmp = gen_reg_rtx (<MODE>mode);
> - emit_insn (gen_copysign<mode>3_soft (operands[0], operands[1],
> - operands[2], tmp));
> - }
> + emit_insn (gen_copysign<mode>3_soft (operands[0], operands[1],
> + operands[2]));
> DONE;
> })
>
> @@ -14125,9 +14122,9 @@ (define_insn "copysign<mode>3_soft"
> [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
> (unspec:IEEE128
> [(match_operand:IEEE128 1 "altivec_register_operand" "v")
> - (match_operand:IEEE128 2 "altivec_register_operand" "v")
> - (match_operand:IEEE128 3 "altivec_register_operand" "+v")]
> - UNSPEC_COPYSIGN))]
> + (match_operand:IEEE128 2 "altivec_register_operand" "v")]
> + UNSPEC_COPYSIGN))
> + (clobber (match_scratch:IEEE128 3 "=&v"))]
> "!TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
> "xscpsgndp %x3,%x2,%x1\;xxpermdi %x0,%x3,%x1,1"
> [(set_attr "type" "veccomplex")
Does this have to be two machine insns for one RTL insns? If you split it
in the expander you don't need the clobber or the earlyclobber or anything
like that.
Okay if splitting it leads to problems elsewhere.
Segher