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[PATCH, GCC/ARM] Fix PR85261: ICE with FPSCR setter builtin
- From: Thomas Preudhomme <thomas dot preudhomme at foss dot arm dot com>
- To: Kyrill Tkachov <kyrylo dot tkachov at arm dot com>, Ramana Radhakrishnan <ramana dot radhakrishnan at arm dot com>, Richard Earnshaw <richard dot earnshaw at arm dot com>, "gcc-patches at gcc dot gnu dot org" <gcc-patches at gcc dot gnu dot org>
- Date: Fri, 6 Apr 2018 16:54:03 +0100
- Subject: [PATCH, GCC/ARM] Fix PR85261: ICE with FPSCR setter builtin
Instruction pattern for setting the FPSCR expects the input value to be
in a register. However, __builtin_arm_set_fpscr expander does not ensure
that this is the case and as a result GCC ICEs when the builtin is
called with a constant literal.
This commit fixes the builtin to force the input value into a register.
It also remove the unneeded volatile in the existing fpscr test and
fixes the function prototype.
ChangeLog entries are as follows:
*** gcc/ChangeLog ***
2018-04-06 Thomas Preud'homme <thomas.preudhomme@arm.com>
PR target/85261
* config/arm/arm-builtins.c (arm_expand_builtin): Force input operand
into register.
*** gcc/testsuite/ChangeLog ***
2018-04-06 Thomas Preud'homme <thomas.preudhomme@arm.com>
PR target/85261
* gcc.target/arm/fpscr.c: Add call to __builtin_arm_set_fpscr with
literal value. Expect 2 MCR instruction. Fix function prototype.
Remove volatile keyword.
Testing: Built an arm-none-eabi GCC cross-compiler and testsuite shows
no regression.
Is this ok for stage4?
Best regards,
Thomas
diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c
index 8940d1f6311bccf86664ab2eaa938735eec595f6..e100d933a77c5de4a13cb961d1bff40f57f2ea80 100644
--- a/gcc/config/arm/arm-builtins.c
+++ b/gcc/config/arm/arm-builtins.c
@@ -2592,7 +2592,7 @@ arm_expand_builtin (tree exp,
icode = CODE_FOR_set_fpscr;
arg0 = CALL_EXPR_ARG (exp, 0);
op0 = expand_normal (arg0);
- pat = GEN_FCN (icode) (op0);
+ pat = GEN_FCN (icode) (force_reg (SImode, op0));
}
emit_insn (pat);
return target;
diff --git a/gcc/testsuite/gcc.target/arm/fpscr.c b/gcc/testsuite/gcc.target/arm/fpscr.c
index 7b4d71d72d8964f6da0d0604bf59aeb4a895df43..4c3eaf7fcf75ad8582071ecb110fd1e4976a3b24 100644
--- a/gcc/testsuite/gcc.target/arm/fpscr.c
+++ b/gcc/testsuite/gcc.target/arm/fpscr.c
@@ -6,11 +6,14 @@
/* { dg-add-options arm_fp } */
void
-test_fpscr ()
+test_fpscr (void)
{
- volatile unsigned int status = __builtin_arm_get_fpscr ();
+ unsigned status;
+
+ __builtin_arm_set_fpscr (0);
+ status = __builtin_arm_get_fpscr ();
__builtin_arm_set_fpscr (status);
}
/* { dg-final { scan-assembler "mrc\tp10, 7, r\[0-9\]+, cr1, cr0, 0" } } */
-/* { dg-final { scan-assembler "mcr\tp10, 7, r\[0-9\]+, cr1, cr0, 0" } } */
+/* { dg-final { scan-assembler-times "mcr\tp10, 7, r\[0-9\]+, cr1, cr0, 0" 2 } } */