PING [PATCH] RX movsicc degrade fix

["Sebastian Perta" <sebastian dot perta at renesas dot com>]

PING

> -----Original Message-----
> From: Sebastian Perta [mailto:sebastian.perta@renesas.com]
> Sent: 09 January 2018 14:46
> To: 'gcc-patches@gcc.gnu.org' <gcc-patches@gcc.gnu.org>
> Subject: [PATCH] RX movsicc degrade fix
> 
> Hello,
> 
> In recent versions of GCC the define_expand "movsicc" has stopped being
> used by GCC (approx. 4.7.x/4.8.x onwards)
> The reason for this is that the first operand of if_then_else has SI mode
and
> it shouldn't have. If we take a look at movsicc for all other targets we
see this
> is true.
> The fix in rx.md is basically a copy paste from v850.md
> 
> The patch also adds a testcase in gcc.target/rx to make sure this degrade
> does not occur again.
> 
> 
> Regression test is OK with one observation (see below), tested with the
> following command:
> make -k check-gcc RUNTESTFLAGS=--target_board=rx-sim
> 
> 
> I have the following fail (which was not present before):
> FAIL: gcc.dg/loop-8.c scan-rtl-dump-times loop2_invariant "Decided" 1
> (found 0 times)
> 
> This is because the patch is effective in this test case and the dump is
not the
> same, I checked the asm code manually and it is OK.
> Is it possible to disable parts of a test case, not the whole test case (*
{ dg-
> final { scan-rtl-dump-times "Decided" 1 "loop2_invariant" } } */  from
loop-8.c
> in this example) for a particular target?
> 
> The total numbers of failures remains the same because the following FAIL
is
> not present anymore with this patch:
> FAIL: gcc.dg/ifcvt-4.c scan-rtl-dump ce1 "2 true changes made"
> 
> 
> Please let me know if this is OK. Thank you!
> 
> Best Regards,
> Sebastian
> 
> 
> Index: ChangeLog
> ==========================================================
> =========
> --- ChangeLog	(revision 256382)
> +++ ChangeLog	(working copy)
> @@ -1,3 +1,8 @@
> +2018-01-09  Sebastian Perta  <sebastian.perta@renesas.com>
> +
> +	*config/rx.md: updated "movsicc" expand to be matched by GCC
> +	*testsuite/gcc.target/rx/movsicc.c: new test case
> +
>  2018-01-09  Richard Biener  <rguenther@suse.de>
> 
>  	PR tree-optimization/83668
> Index: config/rx/rx.md
> ==========================================================
> =========
> --- config/rx/rx.md	(revision 256382)
> +++ config/rx/rx.md	(working copy)
> @@ -733,12 +733,17 @@
>  (define_expand "movsicc"
>    [(parallel
>      [(set (match_operand:SI                  0 "register_operand")
> -	  (if_then_else:SI (match_operand:SI 1 "comparison_operator")
> +	  (if_then_else:SI (match_operand 1 "comparison_operator")
>  			   (match_operand:SI 2 "nonmemory_operand")
>  			   (match_operand:SI 3 "nonmemory_operand")))
>       (clobber (reg:CC CC_REG))])]
>    ""
>  {
> +  /* Make sure that we have an integer comparison...  */
> +  if (GET_MODE (XEXP (operands[1], 0)) != CCmode
> +      && GET_MODE (XEXP (operands[1], 0)) != SImode)
> +    FAIL;
> +
>    /* One operand must be a constant or a register, the other must be a
> register.  */
>    if (   ! CONSTANT_P (operands[2])
>        && ! CONSTANT_P (operands[3])
> Index: testsuite/gcc.target/rx/movsicc.c
> ==========================================================
> =========
> --- testsuite/gcc.target/rx/movsicc.c	(nonexistent)
> +++ testsuite/gcc.target/rx/movsicc.c	(working copy)
> @@ -0,0 +1,94 @@
> +/* { dg-do compile } */
> +/* { dg-options "-Os" } */
> +
> +typedef unsigned char u8;
> +typedef unsigned short u16;
> +signed int Xa, Xb;
> +
> +signed int stzreg_beq(int i, int a, int b)
> +{
> +  signed int x;
> +  x = a;
> +  if (i)
> +    x = b;
> +  return x;
> +}
> +
> +/* { dg-final { scan-assembler "bne 1f" } } */
> +
> +signed int stzreg_bge(int i, int a, int b, int c)
> +{
> +  signed int x;
> +  x = a;
> +  if (i<c)
> +    x = b;
> +  return x;
> +}
> +
> +/* { dg-final { scan-assembler "blt 1f" } } */
> +
> +signed int stzreg_bgt(int i, int a, int b)
> +{
> +  signed int x;
> +  x = a;
> +  if (i<10)
> +    x = b;
> +  return x;
> +}
> +
> +/* { dg-final { scan-assembler "ble 1f" } } */
> +
> +signed int stzreg_ble(int i, int a, int b)
> +{
> +  signed int x;
> +  x = a;
> +  if (i>0)
> +    x = b;
> +  return x;
> +}
> +
> +/* { dg-final { scan-assembler "bgt 1f" } } */
> +
> +signed int stzreg_blt(int i, int a, int b)
> +{
> +  signed int x;
> +  x = a;
> +  if (i<0)
> +    x = b;
> +  return x;
> +}
> +
> +/* { dg-final { scan-assembler "blt 1f" } } */
> +
> +signed int stzreg_bne(int i, int a, int b)
> +{
> +  signed int x;
> +  x = a;
> +  if (!i)
> +    x = b;
> +  return x;
> +}
> +
> +/* { dg-final { scan-assembler "beq 1f" } } */
> +
> +signed int stzimm_le( int i, int a )
> +{
> +  signed int x;
> +  x = a;
> +  if (i>0)
> +    x = 5;
> +  return x;
> +}
> +
> +/* { dg-final { scan-assembler "ble 1f" } } */
> +
> +signed int stzimm_le_r( int i, int a )
> +{
> +  signed int x;
> +  x = a;
> +  if (i<0)
> +    x = 5;
> +  return x;
> +}
> +
> +/* { dg-final { scan-assembler "bge 1f" } } */