[PATCH] PowerPC PR target/84154, fix floating point to small integer conversion regression

[Michael Meissner <meissner at linux dot vnet dot ibm dot com>]

This patch fixes the optimization regression that occurred on GCC 7 where
conversions from the various floating point types to small integers would at
times generate a store and a load.

For example, converting from double to unsigned char generated the following
code on GCC 6 for -mcpu=power8:

        fctiwuz 1,1
        mfvsrd 3,1
        rlwinm 3,3,0,0xff

on GCC 7 and 8 it generates:

        fctiwuz 0,1
        mfvsrwz 9,0
        stw 9,-16(1)
        ori 2,2,0
        lbz 3,-16(1)

The insns before register allocation are:

	(insn 7 8 13 2 (set (subreg:SI (reg:QI 157) 0)
			    (unsigned_fix:SI (reg:SF 33)))

	(insn 13 7 14 2 (set (reg/i:DI 3 3)
			     (zero_extend:DI (reg:QI 157))))

After reload, the insns are:

	(insn 7 8 19 2 (set (reg:SI 32 0 [160])
			    (unsigned_fix:SI (reg:SF 33))))

	(insn 19 7 18 2 (set (reg:SI 9 9 [160])
			     (reg:SI 32 0 [160])))

	(insn 18 19 13 2 (set (mem/c:SI (plus:DI (reg/f:DI 1 1)
						 (const_int -16))
			      (reg:SI 9))))

	(insn 13 18 14 2 (set (reg/i:DI 3 3)
			      (zero_extend:DI (mem/c:HI (plus:DI (reg/f:DI 1 1)
								 (const_int -16))))))

ISA 3.0 (Power9) did not have this problem, because it already had a
fixuns_truncdfqi2 pattern, since QI/HImode values are allowed in vector
registers.  Previous versions of the ISA did not allow QI/HImode into vector
registers, because there wasn't load or store byte/half-word operations.

I extended ISA 3.0 conversion patterns to handle ISA 2.07, using splitters to
move the 32-bit int parts back to the GPR to do sign/zero extension or stores.

I also moved the optimization to prevent the register allocator from doing a
direct move on ISA 3.0 to do an offsettable store via the GPR register to a
separate insn, like I had previously done for SImode.  The rationale for this
is to prevent some places where the register allocator decided to do change a
store into a move (and then later store).

I have tested this patch on a little endian power8 system (64-bit) and a big
endian power8 system (both 32-bit and 64-bit executables).  There were no
regressions in the test suite and the compiler bootstrapped fine.  I added some
tests, and verified they ran in all 3 environments.  Can I check this into the
trunk?  Given this is a regression in GCC 7 as well, can I check the patch if
it applies cleanly into GCC 7 after a burn-in period.

[gcc]
2018-02-01  Michael Meissner  <meissner@linux.vnet.ibm.com>

	PR target/84154
	* config/rs6000/rs6000.md (fix_trunc<SFDF:mode><QHI:mode>2):
	Convert from define_expand to be define_insn_and_split.  Rework
	float/double/_Float128 conversions to QI/HI/SImode to work with
	both ISA 2.07 (power8) or ISA 3.0 (power9).  Fix regression where
	conversions to QI/HImode types did a store and then a load to
	truncate the value.  For conversions to VSX registers, don't split
	the insn, instead emit the code directly.
	(fixuns_trunc<SFDF:mode><QHI:mode>2): Likewise.
	(fix_trunc<IEEE128:mode><QHI:mode>2): Likewise.
	(fix_trunc<SFDF:mode><QHI:mode>2_internal): Delete, no longer
	used.
	(fixuns_trunc<SFDF:mode><QHI:mode>2_internal): Likewise.
	(fix<uns>_<mode>_mem): Likewise.
	(fix_trunc<SFDF:mode><QHI:mode>2_mem): On ISA 3.0, prevent the
	register allocator from doing a direct move to the GPRs to do a
	store, and instead use the ISA 3.0 store byte/half-word from
	vector register instruction.  For IEEE 128-bit floating point,
	also optimize stores of 32-bit ints.
	(fixuns_trunc<SFDF:mode><QHI:mode>2_mem): Likewise.
	(fix_trunc<IEEE128:mode><QHSI:mode>2_mem): Likewise.
	(fixuns_trunc<IEEE128:mode><QHSI:mode>2_mem): Likewise.

[gcc/testsuite]
2018-02-01  Michael Meissner  <meissner@linux.vnet.ibm.com>

	PR target/84154
	* gcc.target/powerpc/pr84154-1.c: New tests.
	* gcc.target/powerpc/pr84154-2.c: Likewise.
	* gcc.target/powerpc/pr84154-3.c: Likewise.

-- 
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.vnet.ibm.com, phone: +1 (978) 899-4797

Attachment: pr84154.patch01b
Description: Text document