Re: [PATCH, rev2], PR target/81550, Disable PRE_{INC,DEC,MODIFY} for VSX floating point

[Michael Meissner <meissner at linux dot vnet dot ibm dot com>]

While we've 'fixed' the loop_align.c test to work with the current compiler, I
did some digging into the effects of subversion id 240482, which removed the
old debug options -m{,no-}upper-regs{,-df,-di,-sf}.  These options controlled
whether the DFmode, DImode, and SFmode types could go into the Altivec
registers.

In subversion id 240481, if you did not use the -mno-upper-regs* switches, on
power7 DFmode and DImode could go into the Altivec registers.  On power8,
SFmode can also go into the Altivec registers.

In subversion id 240481 for power7, the flags in the reg_addr array say that
DFmode does not support ++/-- operations, due to the Altivec registers not
having load and store with update variants.  Similarly for power8, the flags in
the reg_addr for SFmode says that it does not support ++/-- operations.

In subversion id 240482, I allowed ++/-- for DFmode in power7 and ++/-- for
SFmode in power8.

By allowing the ++/-- support for int indexes, it causes IV-OPTS to not
properly optimize the loop.

This patch restores the 240841 behavior of not allowing ++/-- for scalar
floating point types.  The loop looks like:

.L3:
        lfdx 0,4,9
        lfdx 12,5,9
        fadd 0,0,12
        stfdx 0,3,9
        addi 9,9,8
        bdnz .L3

Which is small enough to align the loop to 32 bytes.

However, it does cause slight changes in running Spec 2006 on a little endian
power8 system:

	471.omnetpp:	1.3% faster
	434.zeusmp:	1.9% slower
	435.gromacs:	2.0% faster
	482.sphinx3:	1.4% faster

I did the bootstrap and make check tests, and they all pass.  If I replace the
loop_align.c test with the old version it passes also.  Even with the zeusmp
regression, three other benchmarks speed up slightly, and the simple loop test
also is better.  Can I check this into the trunk?

[gcc]
2018-01-27  Michael Meissner  <meissner@linux.vnet.ibm.com>

	PR target/81550
	* config/rs6000/rs6000.c (rs6000_setup_reg_addr_masks): If
	floating point scalars are allowed in traditional Altivec
	registers, don't allow PRE_{INC,DEC,MODIFY} on those floating
	point types.

-- 
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.vnet.ibm.com, phone: +1 (978) 899-4797

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