This is the mail archive of the gcc-patches@gcc.gnu.org mailing list for the GCC project.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

Re: [PATCH] Misc sse.md formatting fixes


On Thu, Dec 28, 2017 at 10:06 AM, Jakub Jelinek <jakub@redhat.com> wrote:
> Hi!
>
> I've noticed various formatting issues in the recently added ISA support
> patterns.  No functional changes, bootstrapped/regtested on x86_64-linux and
> i686-linux, ok for trunk?
>
> OT, wonder why we have any of the maskz and maskz_1 patterns, can't it be
> done in the intrinsic header by using the mask intrinsic with a _mm*zero*
> operand?  I understand the need to have separate builtins for masked and
> non-masked at least in some cases (as we need AVX512BW for the masked cases
> but not for unmasked).
>
> 2017-12-28  Jakub Jelinek  <jakub@redhat.com>
>
>         * config/i386/sse.md (vgf2p8affineinvqb_<mode><mask_name>,
>         vgf2p8affineqb_<mode><mask_name>, vgf2p8mulb_<mode><mask_name>,
>         vpshrd_<mode><mask_name>, vpshld_<mode><mask_name>,
>         vpshrdv_<mode>, vpshrdv_<mode>_mask, vpshrdv_<mode>_maskz,
>         vpshrdv_<mode>_maskz_1, vpshldv_<mode>, vpshldv_<mode>_mask,
>         vpshldv_<mode>_maskz, vpshldv_<mode>_maskz_1, vpdpbusd_<mode>,
>         vpdpbusd_<mode>_mask, vpdpbusd_<mode>_maskz, vpdpbusd_<mode>_maskz_1,
>         vpdpbusds_<mode>, vpdpbusds_<mode>_mask, vpdpbusds_<mode>_maskz,
>         vpdpbusds_<mode>_maskz_1, vpdpwssd_<mode>, vpdpwssd_<mode>_mask,
>         vpdpwssd_<mode>_maskz, vpdpwssd_<mode>_maskz_1, vpdpwssds_<mode>,
>         vpdpwssds_<mode>_mask, vpdpwssds_<mode>_maskz,
>         vpdpwssds_<mode>_maskz_1, vaesdec_<mode>, vaesdeclast_<mode>,
>         vaesenc_<mode>, vpclmulqdq_<mode>,
>         avx512vl_vpshufbitqmb<mode><mask_scalar_merge_name>): Formatting fixes.

OK as a trivial patch.

Thanks,
Uros.

> --- gcc/config/i386/sse.md.jj   2017-12-22 14:00:04.768613671 +0100
> +++ gcc/config/i386/sse.md      2017-12-27 19:19:58.081660733 +0100
> @@ -20082,10 +20082,11 @@ (define_insn "vpopcount<mode><mask_name>
>
>  (define_insn "vgf2p8affineinvqb_<mode><mask_name>"
>    [(set (match_operand:VI1_AVX512F 0 "register_operand" "=x,x,v")
> -       (unspec:VI1_AVX512F [(match_operand:VI1_AVX512F 1 "register_operand" "%0,x,v")
> -                              (match_operand:VI1_AVX512F 2 "nonimmediate_operand" "xBm,xm,vm")
> -                              (match_operand:QI 3 "const_0_to_255_operand" "n,n,n")]
> -                             UNSPEC_GF2P8AFFINEINV))]
> +       (unspec:VI1_AVX512F
> +         [(match_operand:VI1_AVX512F 1 "register_operand" "%0,x,v")
> +          (match_operand:VI1_AVX512F 2 "nonimmediate_operand" "xBm,xm,vm")
> +          (match_operand:QI 3 "const_0_to_255_operand" "n,n,n")]
> +         UNSPEC_GF2P8AFFINEINV))]
>    "TARGET_GFNI"
>    "@
>     gf2p8affineinvqb\t{%3, %2, %0| %0, %2, %3}
> @@ -20099,10 +20100,11 @@ (define_insn "vgf2p8affineinvqb_<mode><m
>
>  (define_insn "vgf2p8affineqb_<mode><mask_name>"
>    [(set (match_operand:VI1_AVX512F 0 "register_operand" "=x,x,v")
> -       (unspec:VI1_AVX512F [(match_operand:VI1_AVX512F 1 "register_operand" "%0,x,v")
> -                              (match_operand:VI1_AVX512F 2 "nonimmediate_operand" "xBm,xm,vm")
> -                              (match_operand:QI 3 "const_0_to_255_operand" "n,n,n")]
> -                             UNSPEC_GF2P8AFFINE))]
> +       (unspec:VI1_AVX512F
> +         [(match_operand:VI1_AVX512F 1 "register_operand" "%0,x,v")
> +          (match_operand:VI1_AVX512F 2 "nonimmediate_operand" "xBm,xm,vm")
> +          (match_operand:QI 3 "const_0_to_255_operand" "n,n,n")]
> +         UNSPEC_GF2P8AFFINE))]
>    "TARGET_GFNI"
>    "@
>     gf2p8affineqb\t{%3, %2, %0| %0, %2, %3}
> @@ -20116,9 +20118,10 @@ (define_insn "vgf2p8affineqb_<mode><mask
>
>  (define_insn "vgf2p8mulb_<mode><mask_name>"
>    [(set (match_operand:VI1_AVX512F 0 "register_operand" "=x,x,v")
> -       (unspec:VI1_AVX512F [(match_operand:VI1_AVX512F 1 "register_operand" "%0,x,v")
> -                              (match_operand:VI1_AVX512F 2 "nonimmediate_operand" "xBm,xm,vm")]
> -                             UNSPEC_GF2P8MUL))]
> +       (unspec:VI1_AVX512F
> +         [(match_operand:VI1_AVX512F 1 "register_operand" "%0,x,v")
> +          (match_operand:VI1_AVX512F 2 "nonimmediate_operand" "xBm,xm,vm")]
> +         UNSPEC_GF2P8MUL))]
>    "TARGET_GFNI"
>    "@
>     gf2p8mulb\t{%2, %0| %0, %2}
> @@ -20134,9 +20137,9 @@ (define_insn "vpshrd_<mode><mask_name>"
>    [(set (match_operand:VI248_VLBW 0 "register_operand" "=v")
>         (unspec:VI248_VLBW
>           [(match_operand:VI248_VLBW 1 "register_operand" "v")
> -       (match_operand:VI248_VLBW 2 "nonimmediate_operand" "vm")
> -       (match_operand:SI 3 "const_0_to_255_operand" "n")
> -] UNSPEC_VPSHRD))]
> +          (match_operand:VI248_VLBW 2 "nonimmediate_operand" "vm")
> +          (match_operand:SI 3 "const_0_to_255_operand" "n")]
> +         UNSPEC_VPSHRD))]
>    "TARGET_AVX512VBMI2"
>    "vpshrd<ssemodesuffix>\t{%3, %2, %1, %0<mask_operand4>|%0<mask_operand4>, %1, %2, %3 }"
>     [(set_attr ("prefix") ("evex"))])
> @@ -20145,9 +20148,9 @@ (define_insn "vpshld_<mode><mask_name>"
>    [(set (match_operand:VI248_VLBW 0 "register_operand" "=v")
>         (unspec:VI248_VLBW
>           [(match_operand:VI248_VLBW 1 "register_operand" "v")
> -       (match_operand:VI248_VLBW 2 "nonimmediate_operand" "vm")
> -       (match_operand:SI 3 "const_0_to_255_operand" "n")
> -] UNSPEC_VPSHLD))]
> +          (match_operand:VI248_VLBW 2 "nonimmediate_operand" "vm")
> +          (match_operand:SI 3 "const_0_to_255_operand" "n")]
> +         UNSPEC_VPSHLD))]
>    "TARGET_AVX512VBMI2"
>    "vpshld<ssemodesuffix>\t{%3, %2, %1, %0<mask_operand4>|%0<mask_operand4>, %1, %2, %3 }"
>     [(set_attr ("prefix") ("evex"))])
> @@ -20157,8 +20160,8 @@ (define_insn "vpshrdv_<mode>"
>         (unspec:VI248_VLBW
>           [(match_operand:VI248_VLBW 1 "register_operand" "0")
>            (match_operand:VI248_VLBW 2 "register_operand" "v")
> -          (match_operand:VI248_VLBW 3 "nonimmediate_operand" "vm")
> -] UNSPEC_VPSHRDV))]
> +          (match_operand:VI248_VLBW 3 "nonimmediate_operand" "vm")]
> +         UNSPEC_VPSHRDV))]
>    "TARGET_AVX512VBMI2"
>    "vpshrdv<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3 }"
>     [(set_attr ("prefix") ("evex"))
> @@ -20166,14 +20169,14 @@ (define_insn "vpshrdv_<mode>"
>
>  (define_insn "vpshrdv_<mode>_mask"
>    [(set (match_operand:VI248_VLBW 0 "register_operand" "=v")
> -       (vec_merge:VI248_VLBW (unspec:VI248_VLBW
> -         [(match_operand:VI248_VLBW 1 "register_operand" "0")
> -          (match_operand:VI248_VLBW 2 "register_operand" "v")
> -          (match_operand:VI248_VLBW 3 "nonimmediate_operand" "vm")
> -       ] UNSPEC_VPSHRDV)
> -           (match_dup 1)
> -           (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk"))
> -)]
> +       (vec_merge:VI248_VLBW
> +         (unspec:VI248_VLBW
> +           [(match_operand:VI248_VLBW 1 "register_operand" "0")
> +            (match_operand:VI248_VLBW 2 "register_operand" "v")
> +            (match_operand:VI248_VLBW 3 "nonimmediate_operand" "vm")]
> +           UNSPEC_VPSHRDV)
> +         (match_dup 1)
> +         (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))]
>    "TARGET_AVX512VBMI2"
>    "vpshrdv<ssemodesuffix>\t{%3, %2, %0%{%4%}|%0%{%4%}, %2, %3 }"
>     [(set_attr ("prefix") ("evex"))
> @@ -20187,22 +20190,23 @@ (define_expand "vpshrdv_<mode>_maskz"
>     (match_operand:<avx512fmaskmode> 4 "register_operand")]
>    "TARGET_AVX512VBMI2"
>  {
> -  emit_insn (gen_vpshrdv_<mode>_maskz_1 (
> -    operands[0], operands[1], operands[2], operands[3],
> -    CONST0_RTX (<MODE>mode), operands[4]));
> +  emit_insn (gen_vpshrdv_<mode>_maskz_1 (operands[0], operands[1],
> +                                        operands[2], operands[3],
> +                                        CONST0_RTX (<MODE>mode),
> +                                                    operands[4]));
>    DONE;
>  })
>
>  (define_insn "vpshrdv_<mode>_maskz_1"
>    [(set (match_operand:VI248_VLBW 0 "register_operand" "=v")
> -       (vec_merge:VI248_VLBW (unspec:VI248_VLBW
> -         [(match_operand:VI248_VLBW 1 "register_operand" "0")
> -          (match_operand:VI248_VLBW 2 "register_operand" "v")
> -          (match_operand:VI248_VLBW 3 "nonimmediate_operand" "vm")
> -       ] UNSPEC_VPSHRDV)
> +       (vec_merge:VI248_VLBW
> +         (unspec:VI248_VLBW
> +           [(match_operand:VI248_VLBW 1 "register_operand" "0")
> +            (match_operand:VI248_VLBW 2 "register_operand" "v")
> +            (match_operand:VI248_VLBW 3 "nonimmediate_operand" "vm")]
> +           UNSPEC_VPSHRDV)
>           (match_operand:VI248_VLBW 4 "const0_operand" "C")
> -          (match_operand:<avx512fmaskmode> 5 "register_operand" "Yk"))
> -)]
> +         (match_operand:<avx512fmaskmode> 5 "register_operand" "Yk")))]
>    "TARGET_AVX512VBMI2"
>    "vpshrdv<ssemodesuffix>\t{%3, %2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %2, %3 }"
>     [(set_attr ("prefix") ("evex"))
> @@ -20213,8 +20217,8 @@ (define_insn "vpshldv_<mode>"
>         (unspec:VI248_VLBW
>           [(match_operand:VI248_VLBW 1 "register_operand" "0")
>            (match_operand:VI248_VLBW 2 "register_operand" "v")
> -          (match_operand:VI248_VLBW 3 "nonimmediate_operand" "vm")
> -] UNSPEC_VPSHLDV))]
> +          (match_operand:VI248_VLBW 3 "nonimmediate_operand" "vm")]
> +         UNSPEC_VPSHLDV))]
>    "TARGET_AVX512VBMI2"
>    "vpshldv<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3 }"
>     [(set_attr ("prefix") ("evex"))
> @@ -20222,14 +20226,14 @@ (define_insn "vpshldv_<mode>"
>
>  (define_insn "vpshldv_<mode>_mask"
>    [(set (match_operand:VI248_VLBW 0 "register_operand" "=v")
> -       (vec_merge:VI248_VLBW (unspec:VI248_VLBW
> -         [(match_operand:VI248_VLBW 1 "register_operand" "0")
> -          (match_operand:VI248_VLBW 2 "register_operand" "v")
> -          (match_operand:VI248_VLBW 3 "nonimmediate_operand" "vm")
> -       ] UNSPEC_VPSHLDV)
> -          (match_dup 1)
> -          (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk"))
> -)]
> +       (vec_merge:VI248_VLBW
> +         (unspec:VI248_VLBW
> +           [(match_operand:VI248_VLBW 1 "register_operand" "0")
> +            (match_operand:VI248_VLBW 2 "register_operand" "v")
> +            (match_operand:VI248_VLBW 3 "nonimmediate_operand" "vm")]
> +           UNSPEC_VPSHLDV)
> +         (match_dup 1)
> +         (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))]
>    "TARGET_AVX512VBMI2"
>    "vpshldv<ssemodesuffix>\t{%3, %2, %0%{%4%}|%0%{%4%}, %2, %3 }"
>     [(set_attr ("prefix") ("evex"))
> @@ -20243,22 +20247,23 @@ (define_expand "vpshldv_<mode>_maskz"
>     (match_operand:<avx512fmaskmode> 4 "register_operand")]
>    "TARGET_AVX512VBMI2"
>  {
> -  emit_insn (gen_vpshldv_<mode>_maskz_1 (
> -    operands[0], operands[1], operands[2], operands[3],
> -    CONST0_RTX (<MODE>mode), operands[4]));
> +  emit_insn (gen_vpshldv_<mode>_maskz_1 (operands[0], operands[1],
> +                                        operands[2], operands[3],
> +                                        CONST0_RTX (<MODE>mode),
> +                                                    operands[4]));
>    DONE;
>  })
>
>  (define_insn "vpshldv_<mode>_maskz_1"
>    [(set (match_operand:VI248_VLBW 0 "register_operand" "=v")
> -       (vec_merge:VI248_VLBW (unspec:VI248_VLBW
> -         [(match_operand:VI248_VLBW 1 "register_operand" "0")
> -          (match_operand:VI248_VLBW 2 "register_operand" "v")
> -          (match_operand:VI248_VLBW 3 "nonimmediate_operand" "vm")
> -       ] UNSPEC_VPSHLDV)
> +       (vec_merge:VI248_VLBW
> +         (unspec:VI248_VLBW
> +           [(match_operand:VI248_VLBW 1 "register_operand" "0")
> +            (match_operand:VI248_VLBW 2 "register_operand" "v")
> +            (match_operand:VI248_VLBW 3 "nonimmediate_operand" "vm")]
> +           UNSPEC_VPSHLDV)
>           (match_operand:VI248_VLBW 4 "const0_operand" "C")
> -         (match_operand:<avx512fmaskmode> 5 "register_operand" "Yk"))
> -)]
> +         (match_operand:<avx512fmaskmode> 5 "register_operand" "Yk")))]
>    "TARGET_AVX512VBMI2"
>    "vpshldv<ssemodesuffix>\t{%3, %2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %2, %3 }"
>     [(set_attr ("prefix") ("evex"))
> @@ -20269,22 +20274,22 @@ (define_insn "vpdpbusd_<mode>"
>         (unspec:VI4_AVX512VL
>           [(match_operand:VI4_AVX512VL 1 "register_operand" "0")
>            (match_operand:VI4_AVX512VL 2 "register_operand" "v")
> -          (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm")
> -] UNSPEC_VPMADDUBSWACCD))]
> +          (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm")]
> +         UNSPEC_VPMADDUBSWACCD))]
>    "TARGET_AVX512VNNI"
>    "vpdpbusd\t{%3, %2, %0|%0, %2, %3 }"
>     [(set_attr ("prefix") ("evex"))])
>
>  (define_insn "vpdpbusd_<mode>_mask"
>    [(set (match_operand:VI4_AVX512VL 0 "register_operand" "=v")
> -       (vec_merge:VI4_AVX512VL (unspec:VI4_AVX512VL
> -         [(match_operand:VI4_AVX512VL 1 "register_operand" "0")
> -          (match_operand:VI4_AVX512VL 2 "register_operand" "v")
> -          (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm")
> -       ] UNSPEC_VPMADDUBSWACCD)
> -           (match_dup 1)
> -           (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk"))
> -)]
> +       (vec_merge:VI4_AVX512VL
> +         (unspec:VI4_AVX512VL
> +           [(match_operand:VI4_AVX512VL 1 "register_operand" "0")
> +            (match_operand:VI4_AVX512VL 2 "register_operand" "v")
> +            (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm")]
> +           UNSPEC_VPMADDUBSWACCD)
> +         (match_dup 1)
> +         (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))]
>    "TARGET_AVX512VNNI"
>    "vpdpbusd\t{%3, %2, %0%{%4%}|%0%{%4%}, %2, %3 }"
>     [(set_attr ("prefix") ("evex"))])
> @@ -20297,22 +20302,23 @@ (define_expand "vpdpbusd_<mode>_maskz"
>     (match_operand:<avx512fmaskmode> 4 "register_operand")]
>    "TARGET_AVX512VNNI"
>  {
> -  emit_insn (gen_vpdpbusd_<mode>_maskz_1 (
> -    operands[0], operands[1], operands[2], operands[3],
> -    CONST0_RTX (<MODE>mode), operands[4]));
> +  emit_insn (gen_vpdpbusd_<mode>_maskz_1 (operands[0], operands[1],
> +                                         operands[2], operands[3],
> +                                         CONST0_RTX (<MODE>mode),
> +                                                     operands[4]));
>    DONE;
>  })
>
>  (define_insn "vpdpbusd_<mode>_maskz_1"
>    [(set (match_operand:VI4_AVX512VL 0 "register_operand" "=v")
> -       (vec_merge:VI4_AVX512VL (unspec:VI4_AVX512VL
> -         [(match_operand:VI4_AVX512VL 1 "register_operand" "0")
> -          (match_operand:VI4_AVX512VL 2 "register_operand" "v")
> -          (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm")
> -       ] UNSPEC_VPMADDUBSWACCD)
> +       (vec_merge:VI4_AVX512VL
> +         (unspec:VI4_AVX512VL
> +           [(match_operand:VI4_AVX512VL 1 "register_operand" "0")
> +            (match_operand:VI4_AVX512VL 2 "register_operand" "v")
> +            (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm")
> +           ] UNSPEC_VPMADDUBSWACCD)
>           (match_operand:VI4_AVX512VL 4 "const0_operand" "C")
> -          (match_operand:<avx512fmaskmode> 5 "register_operand" "Yk"))
> -)]
> +         (match_operand:<avx512fmaskmode> 5 "register_operand" "Yk")))]
>    "TARGET_AVX512VNNI"
>    "vpdpbusd\t{%3, %2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %2, %3 }"
>     [(set_attr ("prefix") ("evex"))])
> @@ -20323,22 +20329,22 @@ (define_insn "vpdpbusds_<mode>"
>         (unspec:VI4_AVX512VL
>           [(match_operand:VI4_AVX512VL 1 "register_operand" "0")
>            (match_operand:VI4_AVX512VL 2 "register_operand" "v")
> -          (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm")
> -] UNSPEC_VPMADDUBSWACCSSD))]
> +          (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm")]
> +         UNSPEC_VPMADDUBSWACCSSD))]
>    "TARGET_AVX512VNNI"
>    "vpdpbusds\t{%3, %2, %0|%0, %2, %3 }"
>     [(set_attr ("prefix") ("evex"))])
>
>  (define_insn "vpdpbusds_<mode>_mask"
>    [(set (match_operand:VI4_AVX512VL 0 "register_operand" "=v")
> -       (vec_merge:VI4_AVX512VL (unspec:VI4_AVX512VL
> -         [(match_operand:VI4_AVX512VL 1 "register_operand" "0")
> -          (match_operand:VI4_AVX512VL 2 "register_operand" "v")
> -          (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm")
> -       ] UNSPEC_VPMADDUBSWACCSSD)
> -           (match_dup 1)
> -           (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk"))
> -)]
> +       (vec_merge:VI4_AVX512VL
> +         (unspec:VI4_AVX512VL
> +           [(match_operand:VI4_AVX512VL 1 "register_operand" "0")
> +            (match_operand:VI4_AVX512VL 2 "register_operand" "v")
> +            (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm")]
> +           UNSPEC_VPMADDUBSWACCSSD)
> +         (match_dup 1)
> +         (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))]
>    "TARGET_AVX512VNNI"
>    "vpdpbusds\t{%3, %2, %0%{%4%}|%0%{%4%}, %2, %3 }"
>     [(set_attr ("prefix") ("evex"))])
> @@ -20351,22 +20357,23 @@ (define_expand "vpdpbusds_<mode>_maskz"
>     (match_operand:<avx512fmaskmode> 4 "register_operand")]
>    "TARGET_AVX512VNNI"
>  {
> -  emit_insn (gen_vpdpbusds_<mode>_maskz_1 (
> -    operands[0], operands[1], operands[2], operands[3],
> -    CONST0_RTX (<MODE>mode), operands[4]));
> +  emit_insn (gen_vpdpbusds_<mode>_maskz_1 (operands[0], operands[1],
> +                                          operands[2], operands[3],
> +                                          CONST0_RTX (<MODE>mode),
> +                                                      operands[4]));
>    DONE;
>  })
>
>  (define_insn "vpdpbusds_<mode>_maskz_1"
>    [(set (match_operand:VI4_AVX512VL 0 "register_operand" "=v")
> -       (vec_merge:VI4_AVX512VL (unspec:VI4_AVX512VL
> -         [(match_operand:VI4_AVX512VL 1 "register_operand" "0")
> -          (match_operand:VI4_AVX512VL 2 "register_operand" "v")
> -          (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm")
> -       ] UNSPEC_VPMADDUBSWACCSSD)
> +       (vec_merge:VI4_AVX512VL
> +         (unspec:VI4_AVX512VL
> +           [(match_operand:VI4_AVX512VL 1 "register_operand" "0")
> +            (match_operand:VI4_AVX512VL 2 "register_operand" "v")
> +            (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm")]
> +           UNSPEC_VPMADDUBSWACCSSD)
>           (match_operand:VI4_AVX512VL 4 "const0_operand" "C")
> -          (match_operand:<avx512fmaskmode> 5 "register_operand" "Yk"))
> -)]
> +         (match_operand:<avx512fmaskmode> 5 "register_operand" "Yk")))]
>    "TARGET_AVX512VNNI"
>    "vpdpbusds\t{%3, %2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %2, %3 }"
>     [(set_attr ("prefix") ("evex"))])
> @@ -20377,22 +20384,22 @@ (define_insn "vpdpwssd_<mode>"
>         (unspec:VI4_AVX512VL
>           [(match_operand:VI4_AVX512VL 1 "register_operand" "0")
>            (match_operand:VI4_AVX512VL 2 "register_operand" "v")
> -          (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm")
> -] UNSPEC_VPMADDWDACCD))]
> +          (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm")]
> +         UNSPEC_VPMADDWDACCD))]
>    "TARGET_AVX512VNNI"
>    "vpdpwssd\t{%3, %2, %0|%0, %2, %3 }"
>     [(set_attr ("prefix") ("evex"))])
>
>  (define_insn "vpdpwssd_<mode>_mask"
>    [(set (match_operand:VI4_AVX512VL 0 "register_operand" "=v")
> -       (vec_merge:VI4_AVX512VL (unspec:VI4_AVX512VL
> -         [(match_operand:VI4_AVX512VL 1 "register_operand" "0")
> -          (match_operand:VI4_AVX512VL 2 "register_operand" "v")
> -          (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm")
> -       ] UNSPEC_VPMADDWDACCD)
> -           (match_dup 1)
> -           (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk"))
> -)]
> +       (vec_merge:VI4_AVX512VL
> +         (unspec:VI4_AVX512VL
> +           [(match_operand:VI4_AVX512VL 1 "register_operand" "0")
> +            (match_operand:VI4_AVX512VL 2 "register_operand" "v")
> +            (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm")]
> +           UNSPEC_VPMADDWDACCD)
> +         (match_dup 1)
> +         (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))]
>    "TARGET_AVX512VNNI"
>    "vpdpwssd\t{%3, %2, %0%{%4%}|%0%{%4%}, %2, %3 }"
>     [(set_attr ("prefix") ("evex"))])
> @@ -20405,22 +20412,23 @@ (define_expand "vpdpwssd_<mode>_maskz"
>     (match_operand:<avx512fmaskmode> 4 "register_operand")]
>    "TARGET_AVX512VNNI"
>  {
> -  emit_insn (gen_vpdpwssd_<mode>_maskz_1 (
> -    operands[0], operands[1], operands[2], operands[3],
> -    CONST0_RTX (<MODE>mode), operands[4]));
> +  emit_insn (gen_vpdpwssd_<mode>_maskz_1 (operands[0], operands[1],
> +                                         operands[2], operands[3],
> +                                         CONST0_RTX (<MODE>mode),
> +                                                     operands[4]));
>    DONE;
>  })
>
>  (define_insn "vpdpwssd_<mode>_maskz_1"
>    [(set (match_operand:VI4_AVX512VL 0 "register_operand" "=v")
> -       (vec_merge:VI4_AVX512VL (unspec:VI4_AVX512VL
> -         [(match_operand:VI4_AVX512VL 1 "register_operand" "0")
> -          (match_operand:VI4_AVX512VL 2 "register_operand" "v")
> -          (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm")
> -       ] UNSPEC_VPMADDWDACCD)
> +       (vec_merge:VI4_AVX512VL
> +         (unspec:VI4_AVX512VL
> +           [(match_operand:VI4_AVX512VL 1 "register_operand" "0")
> +            (match_operand:VI4_AVX512VL 2 "register_operand" "v")
> +            (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm")]
> +           UNSPEC_VPMADDWDACCD)
>           (match_operand:VI4_AVX512VL 4 "const0_operand" "C")
> -          (match_operand:<avx512fmaskmode> 5 "register_operand" "Yk"))
> -)]
> +         (match_operand:<avx512fmaskmode> 5 "register_operand" "Yk")))]
>    "TARGET_AVX512VNNI"
>    "vpdpwssd\t{%3, %2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %2, %3 }"
>     [(set_attr ("prefix") ("evex"))])
> @@ -20431,22 +20439,22 @@ (define_insn "vpdpwssds_<mode>"
>         (unspec:VI4_AVX512VL
>           [(match_operand:VI4_AVX512VL 1 "register_operand" "0")
>            (match_operand:VI4_AVX512VL 2 "register_operand" "v")
> -          (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm")
> -] UNSPEC_VPMADDWDACCSSD))]
> +          (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm")]
> +         UNSPEC_VPMADDWDACCSSD))]
>    "TARGET_AVX512VNNI"
>    "vpdpwssds\t{%3, %2, %0|%0, %2, %3 }"
>     [(set_attr ("prefix") ("evex"))])
>
>  (define_insn "vpdpwssds_<mode>_mask"
>    [(set (match_operand:VI4_AVX512VL 0 "register_operand" "=v")
> -       (vec_merge:VI4_AVX512VL (unspec:VI4_AVX512VL
> -         [(match_operand:VI4_AVX512VL 1 "register_operand" "0")
> -          (match_operand:VI4_AVX512VL 2 "register_operand" "v")
> -          (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm")
> -       ] UNSPEC_VPMADDWDACCSSD)
> -           (match_dup 1)
> -           (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk"))
> -)]
> +       (vec_merge:VI4_AVX512VL
> +         (unspec:VI4_AVX512VL
> +           [(match_operand:VI4_AVX512VL 1 "register_operand" "0")
> +            (match_operand:VI4_AVX512VL 2 "register_operand" "v")
> +            (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm")]
> +           UNSPEC_VPMADDWDACCSSD)
> +         (match_dup 1)
> +         (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))]
>    "TARGET_AVX512VNNI"
>    "vpdpwssds\t{%3, %2, %0%{%4%}|%0%{%4%}, %2, %3 }"
>     [(set_attr ("prefix") ("evex"))])
> @@ -20459,29 +20467,30 @@ (define_expand "vpdpwssds_<mode>_maskz"
>     (match_operand:<avx512fmaskmode> 4 "register_operand")]
>    "TARGET_AVX512VNNI"
>  {
> -  emit_insn (gen_vpdpwssds_<mode>_maskz_1 (
> -    operands[0], operands[1], operands[2], operands[3],
> -    CONST0_RTX (<MODE>mode), operands[4]));
> +  emit_insn (gen_vpdpwssds_<mode>_maskz_1 (operands[0], operands[1],
> +                                          operands[2], operands[3],
> +                                          CONST0_RTX (<MODE>mode),
> +                                                      operands[4]));
>    DONE;
>  })
>
>  (define_insn "vpdpwssds_<mode>_maskz_1"
>    [(set (match_operand:VI4_AVX512VL 0 "register_operand" "=v")
> -       (vec_merge:VI4_AVX512VL (unspec:VI4_AVX512VL
> -         [(match_operand:VI4_AVX512VL 1 "register_operand" "0")
> -          (match_operand:VI4_AVX512VL 2 "register_operand" "v")
> -          (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm")
> -       ] UNSPEC_VPMADDWDACCSSD)
> +       (vec_merge:VI4_AVX512VL
> +         (unspec:VI4_AVX512VL
> +           [(match_operand:VI4_AVX512VL 1 "register_operand" "0")
> +            (match_operand:VI4_AVX512VL 2 "register_operand" "v")
> +            (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm")]
> +           UNSPEC_VPMADDWDACCSSD)
>           (match_operand:VI4_AVX512VL 4 "const0_operand" "C")
> -          (match_operand:<avx512fmaskmode> 5 "register_operand" "Yk"))
> -)]
> +         (match_operand:<avx512fmaskmode> 5 "register_operand" "Yk")))]
>    "TARGET_AVX512VNNI"
>    "vpdpwssds\t{%3, %2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %2, %3 }"
>     [(set_attr ("prefix") ("evex"))])
>
>  (define_insn "vaesdec_<mode>"
>    [(set (match_operand:VI1_AVX512VL_F 0 "register_operand" "=v")
> -         (unspec:VI1_AVX512VL_F
> +       (unspec:VI1_AVX512VL_F
>           [(match_operand:VI1_AVX512VL_F 1 "register_operand" "v")
>            (match_operand:VI1_AVX512VL_F 2 "vector_operand" "v")]
>           UNSPEC_VAESDEC))]
> @@ -20491,7 +20500,7 @@ (define_insn "vaesdec_<mode>"
>
>  (define_insn "vaesdeclast_<mode>"
>    [(set (match_operand:VI1_AVX512VL_F 0 "register_operand" "=v")
> -         (unspec:VI1_AVX512VL_F
> +       (unspec:VI1_AVX512VL_F
>           [(match_operand:VI1_AVX512VL_F 1 "register_operand" "v")
>            (match_operand:VI1_AVX512VL_F 2 "vector_operand" "v")]
>           UNSPEC_VAESDECLAST))]
> @@ -20501,7 +20510,7 @@ (define_insn "vaesdeclast_<mode>"
>
>  (define_insn "vaesenc_<mode>"
>    [(set (match_operand:VI1_AVX512VL_F 0 "register_operand" "=v")
> -         (unspec:VI1_AVX512VL_F
> +       (unspec:VI1_AVX512VL_F
>           [(match_operand:VI1_AVX512VL_F 1 "register_operand" "v")
>            (match_operand:VI1_AVX512VL_F 2 "vector_operand" "vm")]
>           UNSPEC_VAESENC))]
> @@ -20511,7 +20520,7 @@ (define_insn "vaesenc_<mode>"
>
>  (define_insn "vaesenclast_<mode>"
>    [(set (match_operand:VI1_AVX512VL_F 0 "register_operand" "=v")
> -         (unspec:VI1_AVX512VL_F
> +       (unspec:VI1_AVX512VL_F
>           [(match_operand:VI1_AVX512VL_F 1 "register_operand" "v")
>            (match_operand:VI1_AVX512VL_F 2 "vector_operand" "vm")]
>           UNSPEC_VAESENCLAST))]
> @@ -20522,9 +20531,9 @@ (define_insn "vaesenclast_<mode>"
>  (define_insn "vpclmulqdq_<mode>"
>    [(set (match_operand:VI8_FVL 0 "register_operand" "=v")
>         (unspec:VI8_FVL [(match_operand:VI8_FVL 1 "register_operand" "v")
> -                     (match_operand:VI8_FVL 2 "vector_operand" "vm")
> -                     (match_operand:SI 3 "const_0_to_255_operand" "n")]
> -                    UNSPEC_VPCLMULQDQ))]
> +                        (match_operand:VI8_FVL 2 "vector_operand" "vm")
> +                        (match_operand:SI 3 "const_0_to_255_operand" "n")]
> +                       UNSPEC_VPCLMULQDQ))]
>    "TARGET_VPCLMULQDQ"
>    "vpclmulqdq\t{%3, %2, %1, %0|%0, %1, %2, %3}"
>    [(set_attr "mode" "DI")])
> @@ -20534,7 +20543,7 @@ (define_insn "avx512vl_vpshufbitqmb<mode
>         (unspec:<avx512fmaskmode>
>           [(match_operand:VI48_AVX512VLBW 1 "register_operand" "v")
>            (match_operand:VI48_AVX512VLBW 2 "nonimmediate_operand" "vm")]
> -       UNSPEC_VPSHUFBIT))]
> +         UNSPEC_VPSHUFBIT))]
>    "TARGET_AVX512BITALG"
>    "vpshufbitqmb\t{%2, %1, %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %2}"
>    [(set_attr "prefix" "evex")
>
>         Jakub


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]