Re: [Patch combine] Don't create vector mode ZERO_EXTEND from subregs

[James Greenhalgh <james dot greenhalgh at arm dot com>]

On Sun, Dec 17, 2017 at 03:14:08AM +0000, Segher Boessenkool wrote:
> Hi!
>
> On Mon, Dec 11, 2017 at 02:18:53PM +0000, James Greenhalgh wrote:
> >
> > In simplify_set we try transforming the paradoxical subreg expression:
> >
> >   (set FOO (subreg:M (mem:N BAR) 0))
> >
> > in to:
> >
> >   (set FOO (zero_extend:M (mem:N BAR)))
> >
> > However, this code does not consider the case where M is a vector
> > mode, allowing it to construct (for example):
> >
> >   (zero_extend:V4SI (mem:SI))
> >
> > This would clearly have the wrong semantics, but fortunately we fail long
> > before then in expand_compound_operation. As we really don't want a vector
> > zero_extend of a scalar value.
> >
> > We need to explicitly reject vector modes from this transformation.
>
> It does not consider any other modes either.  Both modes involved are
> required to be SCALAR_INT_MODE_P (for zero_extend to be valid at all and
> to be equivalent to the subreg); could you test for that instead please?

Makes sense. I've committed this as obvious after an AArch64 bootstrap and
test as revision 255945.

Thanks,
James

---
gcc/

2017-12-21  James Greenhalgh  <james.greenhalgh@arm.com>

	* combine.c (simplify_set): Do not transform subregs to zero_extends
	if the destination is not a scalar int mode.

diff --git a/gcc/combine.c b/gcc/combine.c
index 9f19ee4..91bed06 100644
--- a/gcc/combine.c
+++ b/gcc/combine.c
@@ -6967,12 +6967,13 @@ simplify_set (rtx x)
   /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
      would require a paradoxical subreg.  Replace the subreg with a
      zero_extend to avoid the reload that would otherwise be required.
-     Don't do this for vector modes, as the transformation is incorrect.  */
+     Don't do this unless we have a scalar integer mode, otherwise the
+     transformation is incorrect.  */
 
   enum rtx_code extend_op;
   if (paradoxical_subreg_p (src)
       && MEM_P (SUBREG_REG (src))
-      && !VECTOR_MODE_P (GET_MODE (src))
+      && SCALAR_INT_MODE_P (GET_MODE (src))
       && (extend_op = load_extend_op (GET_MODE (SUBREG_REG (src)))) != UNKNOWN)
     {
       SUBST (SET_SRC (x),