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[PATCH], Generate XXBR{H,W,D} for bswap{16,32,64} on PowerPC ISA 3.0 (power9)


PowerPC ISA 3.0 does not have a byte-reverse instruction that operates on the
GPRs, but it does have vector byte swap half-word, word, double-word operations
in the VSX registers.  The enclosed patch enables generation of the byte
revseral instructions for register-register operations.  It still prefers to
generate the load with byte reverse (L{H,W,D}BRX) or store with byte reverse
(ST{H,W,D}BRX) instructions over the register sequence.

For 16-bit and 32-bit byte swaps, it typically does the tradational operation
in GPR registers, but it will generate XXBR{H,W} if the values are in vector
registers.

For 64-bit swaps, it no longer generates the 9 instruction sequence in favor of
XXBRD.  I did some timing runs on a prototype power9 system, and it was
slightly faster to do direct move to the vecter unit, XXBRD, and direct move
back to a GPR than the traditional sequence.

I did bootstraps on little endian Power8 and Power9 systems (with the default
cpu set to power8 and power9 respectively).  There were no regressions.  Can I
check this patch into the trunk?

[gcc]
2017-11-08  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* config/rs6000/rs6000.md (bswaphi2_reg): On ISA 3.0 systems,
	enable generating XXBR{H,W} if the value is in a vector
	register.
	(bswapsi2_reg): Likewise.
	(bswapdi2_reg): On ISA 3.0 systems, use XXBRD to do bswap64
	instead of doing the GPR sequence used on previoius machines.
	(bswapdi2_xxbrd): Likewise.
	(bswapdi2_reg splitters): Use int_reg_operand instead of
	gpc_reg_operand to not match when XXBRD is generated.

[gcc/testsuite]
2017-11-08  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* gcc.target/powerpc/p9-xxbr-3.c: New test.

-- 
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.vnet.ibm.com, phone: +1 (978) 899-4797

Attachment: gcc-power9.patch300b
Description: Text document


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