RE: [patch][x86] GFNI enabling [2/4]

["Koval, Julia" <julia dot koval at intel dot com>]

Here is the solution I propose:

gcc/
	* common/config/i386/i386-common.c
	(OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET): Remove MPX from flag.
	(ix86_handle_option): Move MPX to isa_flags2 and GFNI to isa_flags.
	* config/i386/i386-c.c (ix86_target_macros_internal): Ditto.
	* config/i386/i386.opt: Ditto.
	* config/i386/i386.c (ix86_target_string): Ditto.
	(ix86_option_override_internal): Ditto.
	(ix86_init_mpx_builtins): Move MPX to args2.
	(ix86_expand_builtin): Special handling for OPTION_MASK_ISA_GFNI.
	* config/i386/i386-builtin.def (__builtin_ia32_vgf2p8affineinvqb_v64qi,
	__builtin_ia32_vgf2p8affineinvqb_v64qi_mask,
	__builtin_ia32_vgf2p8affineinvqb_v32qi,
	__builtin_ia32_vgf2p8affineinvqb_v32qi_mask,
	__builtin_ia32_vgf2p8affineinvqb_v16qi,
	__builtin_ia32_vgf2p8affineinvqb_v16qi_mask): Move to ARGS array.

> -----Original Message-----
> From: Koval, Julia
> Sent: Friday, November 03, 2017 9:27 AM
> To: 'Jakub Jelinek' <jakub@redhat.com>
> Cc: 'Kirill Yukhin' <kirill.yukhin@gmail.com>; 'GCC Patches' <gcc-
> patches@gcc.gnu.org>
> Subject: RE: [patch][x86] GFNI enabling [2/4]
> 
> > But what do you think about adding AVX/SSE flags to this special set instead?
> Ok, was wrong, it is impossible to add SSE, because it is used in normal "or" way.
> Then I'll add GFNI/VAES instead.
> 
> There is also another problem there: GFNI belongs to isa_flags2, while
> AVX512VL/AVX/SSE belong to isa_flags, so we can't keep them in the same field.
> There are candidates, which can be moved from isa_flags to isa_flags2 instead
> of GFNI, because there are no dependencies on other flags, but it is only a short
> term solution.
> 
> > -----Original Message-----
> > From: Koval, Julia
> > Sent: Thursday, November 02, 2017 12:57 PM
> > To: Jakub Jelinek <jakub@redhat.com>
> > Cc: Kirill Yukhin <kirill.yukhin@gmail.com>; GCC Patches <gcc-
> > patches@gcc.gnu.org>
> > Subject: RE: [patch][x86] GFNI enabling [2/4]
> >
> > The documentation is right, I was wrong not adding SSE/AVX flags in these
> > builtin declaratuin.
> >
> > > The exceptions are
> > > MMX, AVX512VL and 64BIT is also special.
> > > So, shall GFNI be added to that set?
> > Turns out only GFNI and VAES(haven't sent those yet, they are from the same
> > Icelake pdf) are like this, others rely on AVX512VL/BW. But what do you think
> > about adding AVX/SSE flags to this special set instead? Looks like they more
> > probably will be used as a flags, on which new instructions may depend in the
> > future, than GFNI/VAES flags.
> >
> > -Julia
> >
> > > -----Original Message-----
> > > From: gcc-patches-owner@gcc.gnu.org [mailto:gcc-patches-
> > > owner@gcc.gnu.org] On Behalf Of Jakub Jelinek
> > > Sent: Tuesday, October 31, 2017 8:28 PM
> > > To: Koval, Julia <julia.koval@intel.com>
> > > Cc: Kirill Yukhin <kirill.yukhin@gmail.com>; GCC Patches <gcc-
> > > patches@gcc.gnu.org>
> > > Subject: Re: [patch][x86] GFNI enabling [2/4]
> > >
> > > On Mon, Oct 30, 2017 at 07:02:23PM +0000, Koval, Julia wrote:
> > > > gcc/testsuite/
> > > > 	* gcc.target/i386/avx-1.c: Handle new intrinsics.
> > > > 	* gcc.target/i386/avx512-check.h: Check GFNI bit.
> > > > 	* gcc.target/i386/avx512f-gf2p8affineinvqb-2.c: Runtime test.
> > > > 	* gcc.target/i386/avx512vl-gf2p8affineinvqb-2.c: Runtime test.
> > > > 	* gcc.target/i386/gfni-1.c: New.
> > > > 	* gcc.target/i386/gfni-2.c: New.
> > > > 	* gcc.target/i386/gfni-3.c: New.
> > > > 	* gcc.target/i386/gfni-4.c: New.
> > >
> > > The gfni-4.c testcase ICEs on i686-linux (e.g. try
> > > make check-gcc RUNTESTFLAGS='--target_board=unix\{-m32/-msse,-m32/-
> > > mno-sse,-m64\} i386.exp=gfni*'
> > > to see it).
> > >
> > > I must say I'm confused by the CPUIDs, the
> > > https://software.intel.com/sites/default/files/managed/c5/15/architecture-
> > > instruction-set-extensions-programming-reference.pdf
> > > lists GFNI; 2x AVX+GFNI; 2x AVX512VL+GFNI; AVX512F+GFNI CPUIDs for the
> > > instructions, but i386-builtins.def has:
> > > BDESC (OPTION_MASK_ISA_GFNI, CODE_FOR_vgf2p8affineinvqb_v64qi,
> > > "__builtin_ia32_vgf2p8affineinvqb_v64qi",
> > > IX86_BUILTIN_VGF2P8AFFINEINVQB512, UNKNOWN
> > > BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_AVX512BW,
> > > CODE_FOR_vgf2p8affineinvqb_v64qi_mask,
> > > "__builtin_ia32_vgf2p8affineinvqb_v64qi_mask", IX86_
> > > BDESC (OPTION_MASK_ISA_GFNI, CODE_FOR_vgf2p8affineinvqb_v32qi,
> > > "__builtin_ia32_vgf2p8affineinvqb_v32qi",
> > > IX86_BUILTIN_VGF2P8AFFINEINVQB256, UNKNOWN
> > > BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_AVX512BW,
> > > CODE_FOR_vgf2p8affineinvqb_v32qi_mask,
> > > "__builtin_ia32_vgf2p8affineinvqb_v32qi_mask", IX86_
> > > BDESC (OPTION_MASK_ISA_GFNI, CODE_FOR_vgf2p8affineinvqb_v16qi,
> > > "__builtin_ia32_vgf2p8affineinvqb_v16qi",
> > > IX86_BUILTIN_VGF2P8AFFINEINVQB128, UNKNOWN
> > > BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_AVX512BW,
> > > CODE_FOR_vgf2p8affineinvqb_v16qi_mask,
> > > "__builtin_ia32_vgf2p8affineinvqb_v16qi_mask", IX86_
> > > and the gfniintrin.h requires just gfni for the first insn,
> > > and then some combinations of gfni,avx, or gfni,avx512vl, or
> > > gfni,avx512vl,avx512bw, or gfni,avx512f,avx512bw.
> > >
> > > So, what is right, the paper, i386-builtins.def or gfniintrin.h?
> > >
> > > Obviously even if the GF2P8AFFINEINVQB instruction doesn't list SSE as
> > > required CPUID, we can't really emit it without at least SSE because
> > > then the operands can't be emitted.  So, at least in GCC we should
> > > require both GFNI and SSE for the first instruction.
> > >
> > > Which leads to another issue, as ix86_expand_builtin documents,
> > > we treat the BDESC ISAs OPTION_MASK_ISA_ISA1 | OPTION_MASK_ISA_ISA2
> > > as either ISA1 or ISA2, not ISA1 and ISA2.  The exceptions are
> > > MMX, AVX512VL and 64BIT is also special.
> > > So, shall GFNI be added to that set?  Do we have other ISAs that
> > > should be handled the same?  I guess maybe OPTION_MASK_ISA_AES, but
> > > that is handled weirdly.
> > >
> > > 	Jakub

Attachment: 0001-fix-gfni.patch
Description: 0001-fix-gfni.patch