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[PATCH][Arm] Cleanup IT attributes
- From: Wilco Dijkstra <Wilco dot Dijkstra at arm dot com>
- To: GCC Patches <gcc-patches at gcc dot gnu dot org>
- Cc: nd <nd at arm dot com>
- Date: Fri, 3 Nov 2017 14:38:56 +0000
- Subject: [PATCH][Arm] Cleanup IT attributes
- Authentication-results: sourceware.org; auth=none
- Authentication-results: spf=none (sender IP is ) smtp.mailfrom=Wilco dot Dijkstra at arm dot com;
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A recent change to remove the movdi_vfp_cortexa8 meant that ldrd was used in
ITs block even when arm_restrict_it was enabled. Rather than just fixing this
latent issue, change the default of predicable_short_it to "no" so that only
16-bit instructions need to be marked with it. As a result there are far fewer
patterns that need the attribute, and omitting predicable_short_it is no longer
causing issues.
This fixes 4 tests that failed after r254233, OK for commit?
ChangeLog:
2017-11-03 Wilco Dijkstra <wdijkstr@arm.com>
* config/arm/arm.md (predicable_short_it): Change default to "no",
improve documentation, remove uses that are identical to the default.
(enabled_for_depr_it): Rename to enabled_for_short_it.
* config/arm/arm-fixed.md (predicable_short_it): Remove default uses.
* config/arm/ldmstm.md (predicable_short_it): Likewise.
* config/arm/sync.md (predicable_short_it): Likewise.
* config/arm/thumb2.md (predicable_short_it): Likewise.
* config/arm/vfp.md (predicable_short_it): Likewise.
--
diff --git a/gcc/config/arm/arm-fixed.md b/gcc/config/arm/arm-fixed.md
index ca721437792c7e3ad4fdc5ab5701aa79f01932cb..6730a2bbad6b107c669cb003cfdb651243740553 100644
--- a/gcc/config/arm/arm-fixed.md
+++ b/gcc/config/arm/arm-fixed.md
@@ -35,7 +35,6 @@
"TARGET_INT_SIMD"
"sadd<qaddsub_suf>%?\\t%0, %1, %2"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "alu_dsp_reg")])
(define_insn "usadd<mode>3"
@@ -45,7 +44,6 @@
"TARGET_INT_SIMD"
"uqadd<qaddsub_suf>%?\\t%0, %1, %2"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "alu_dsp_reg")])
(define_insn "ssadd<mode>3"
@@ -55,7 +53,6 @@
"TARGET_INT_SIMD"
"qadd<qaddsub_suf>%?\\t%0, %1, %2"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "alu_dsp_reg")])
(define_insn "sub<mode>3"
@@ -75,7 +72,6 @@
"TARGET_INT_SIMD"
"ssub<qaddsub_suf>%?\\t%0, %1, %2"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "alu_dsp_reg")])
(define_insn "ussub<mode>3"
@@ -86,7 +82,6 @@
"TARGET_INT_SIMD"
"uqsub<qaddsub_suf>%?\\t%0, %1, %2"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "alu_dsp_reg")])
(define_insn "sssub<mode>3"
@@ -96,7 +91,6 @@
"TARGET_INT_SIMD"
"qsub<qaddsub_suf>%?\\t%0, %1, %2"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "alu_dsp_reg")])
;; Fractional multiplies.
@@ -414,7 +408,6 @@
"TARGET_32BIT && arm_arch6"
"ssat%?\\t%0, #16, %2%S1"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "shift" "1")
(set_attr "type" "alu_shift_imm")])
@@ -424,6 +417,5 @@
"TARGET_INT_SIMD"
"usat%?\\t%0, #16, %1"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "alu_imm")]
)
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 22a264b53dcb8dffe62da77ebd7420e1484de42d..e2d528442b49f816e854acb3945413b4e5fcc3a8 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -81,14 +81,17 @@
(const (if_then_else (symbol_ref "TARGET_THUMB1")
(const_string "yes") (const_string "no"))))
-; We use this attribute to disable alternatives that can produce 32-bit
-; instructions inside an IT-block in Thumb2 state. ARMv8 deprecates IT blocks
-; that contain 32-bit instructions.
-(define_attr "enabled_for_depr_it" "no,yes" (const_string "yes"))
-
-; This attribute is used to disable a predicated alternative when we have
-; arm_restrict_it.
-(define_attr "predicable_short_it" "no,yes" (const_string "yes"))
+; Mark an instruction as suitable for "short IT" blocks in Thumb-2.
+; The arm_restrict_it flag enables the "short IT" feature which
+; restricts IT blocks to a single 16-bit instruction.
+; This attribute should only be used on 16-bit Thumb-2 instructions
+; which may be predicated (the "predicable" attribute must be set).
+(define_attr "predicable_short_it" "no,yes" (const_string "no"))
+
+; Mark an instruction as suitable for "short IT" blocks in Thumb-2.
+; This attribute should only be used on instructions which may emit
+; an IT block in their expansion which is not a short IT.
+(define_attr "enabled_for_short_it" "no,yes" (const_string "yes"))
;; Operand number of an input operand that is shifted. Zero if the
;; given instruction does not shift one of its input operands.
@@ -229,7 +232,7 @@
(match_test "arm_restrict_it")))
(const_string "no")
- (and (eq_attr "enabled_for_depr_it" "no")
+ (and (eq_attr "enabled_for_short_it" "no")
(match_test "arm_restrict_it"))
(const_string "no")
@@ -1031,7 +1034,6 @@
"adc%?\\t%0, %1, %3%S2"
[(set_attr "conds" "use")
(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "")
(const_string "alu_shift_imm")
(const_string "alu_shift_reg")))]
@@ -1135,7 +1137,6 @@
[(set_attr "conds" "use")
(set_attr "arch" "*,a,t2")
(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "adc_reg,adc_imm,alu_shift_imm")]
)
@@ -1669,8 +1670,7 @@
"TARGET_32BIT && arm_arch6"
"mla%?\\t%0, %2, %1, %3"
[(set_attr "type" "mla")
- (set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")]
+ (set_attr "predicable" "yes")]
)
(define_insn "*mulsi3addsi_compare0"
@@ -1746,8 +1746,7 @@
"TARGET_32BIT && arm_arch_thumb2"
"mls%?\\t%0, %2, %1, %3"
[(set_attr "type" "mla")
- (set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")]
+ (set_attr "predicable" "yes")]
)
(define_expand "maddsidi4"
@@ -1783,8 +1782,7 @@
"TARGET_32BIT && arm_arch6"
"smlal%?\\t%Q0, %R0, %3, %2"
[(set_attr "type" "smlal")
- (set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")]
+ (set_attr "predicable" "yes")]
)
;; 32x32->64 widening multiply.
@@ -1821,8 +1819,7 @@
"TARGET_32BIT && arm_arch6"
"smull%?\\t%Q0, %R0, %1, %2"
[(set_attr "type" "smull")
- (set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")]
+ (set_attr "predicable" "yes")]
)
(define_expand "umulsidi3"
@@ -1853,8 +1850,7 @@
"TARGET_32BIT && arm_arch6"
"umull%?\\t%Q0, %R0, %1, %2"
[(set_attr "type" "umull")
- (set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")]
+ (set_attr "predicable" "yes")]
)
(define_expand "umaddsidi4"
@@ -1890,8 +1886,7 @@
"TARGET_32BIT && arm_arch6"
"umlal%?\\t%Q0, %R0, %3, %2"
[(set_attr "type" "umlal")
- (set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")]
+ (set_attr "predicable" "yes")]
)
(define_expand "smulsi3_highpart"
@@ -1935,8 +1930,7 @@
"TARGET_32BIT && arm_arch6"
"smull%?\\t%3, %0, %2, %1"
[(set_attr "type" "smull")
- (set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")]
+ (set_attr "predicable" "yes")]
)
(define_expand "umulsi3_highpart"
@@ -1980,8 +1974,7 @@
"TARGET_32BIT && arm_arch6"
"umull%?\\t%3, %0, %2, %1"
[(set_attr "type" "umull")
- (set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")]
+ (set_attr "predicable" "yes")]
)
(define_insn "mulhisi3"
@@ -2006,8 +1999,7 @@
"TARGET_DSP_MULTIPLY"
"smultb%?\\t%0, %1, %2"
[(set_attr "type" "smulxy")
- (set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")]
+ (set_attr "predicable" "yes")]
)
(define_insn "*mulhisi3bt"
@@ -2020,8 +2012,7 @@
"TARGET_DSP_MULTIPLY"
"smulbt%?\\t%0, %1, %2"
[(set_attr "type" "smulxy")
- (set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")]
+ (set_attr "predicable" "yes")]
)
(define_insn "*mulhisi3tt"
@@ -2035,8 +2026,7 @@
"TARGET_DSP_MULTIPLY"
"smultt%?\\t%0, %1, %2"
[(set_attr "type" "smulxy")
- (set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")]
+ (set_attr "predicable" "yes")]
)
(define_insn "maddhisi4"
@@ -2049,8 +2039,7 @@
"TARGET_DSP_MULTIPLY"
"smlabb%?\\t%0, %1, %2, %3"
[(set_attr "type" "smlaxy")
- (set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")]
+ (set_attr "predicable" "yes")]
)
;; Note: there is no maddhisi4ibt because this one is canonical form
@@ -2065,8 +2054,7 @@
"TARGET_DSP_MULTIPLY"
"smlatb%?\\t%0, %1, %2, %3"
[(set_attr "type" "smlaxy")
- (set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")]
+ (set_attr "predicable" "yes")]
)
(define_insn "*maddhisi4tt"
@@ -2081,8 +2069,7 @@
"TARGET_DSP_MULTIPLY"
"smlatt%?\\t%0, %1, %2, %3"
[(set_attr "type" "smlaxy")
- (set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")]
+ (set_attr "predicable" "yes")]
)
(define_insn "maddhidi4"
@@ -2096,8 +2083,7 @@
"TARGET_DSP_MULTIPLY"
"smlalbb%?\\t%Q0, %R0, %1, %2"
[(set_attr "type" "smlalxy")
- (set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")])
+ (set_attr "predicable" "yes")])
;; Note: there is no maddhidi4ibt because this one is canonical form
(define_insn "*maddhidi4tb"
@@ -2113,8 +2099,7 @@
"TARGET_DSP_MULTIPLY"
"smlaltb%?\\t%Q0, %R0, %1, %2"
[(set_attr "type" "smlalxy")
- (set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")])
+ (set_attr "predicable" "yes")])
(define_insn "*maddhidi4tt"
[(set (match_operand:DI 0 "s_register_operand" "=r")
@@ -2131,8 +2116,7 @@
"TARGET_DSP_MULTIPLY"
"smlaltt%?\\t%Q0, %R0, %1, %2"
[(set_attr "type" "smlalxy")
- (set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")])
+ (set_attr "predicable" "yes")])
(define_expand "mulsf3"
[(set (match_operand:SF 0 "s_register_operand" "")
@@ -2519,7 +2503,6 @@
"
[(set_attr "conds" "set")
(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "logics_imm")]
)
@@ -2919,7 +2902,6 @@
"bfc%?\t%0, %2, %1"
[(set_attr "length" "4")
(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "bfm")]
)
@@ -2932,7 +2914,6 @@
"bfi%?\t%0, %3, %2, %1"
[(set_attr "length" "4")
(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "bfm")]
)
@@ -2985,7 +2966,6 @@
}"
[(set_attr "length" "4,8")
(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "multiple")]
)
@@ -3007,7 +2987,6 @@
}"
[(set_attr "length" "8")
(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "multiple")]
)
@@ -3032,7 +3011,6 @@
}"
[(set_attr "length" "8")
(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "multiple")]
)
@@ -3043,7 +3021,6 @@
"TARGET_32BIT"
"bic%?\\t%0, %1, %2"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "logic_reg")]
)
@@ -3077,7 +3054,6 @@
"TARGET_ARM || (TARGET_THUMB2 && CONST_INT_P (operands[2]))"
"bics%?\\t%4, %3, %1%S0"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "conds" "set")
(set_attr "shift" "1")
(set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
@@ -3103,7 +3079,6 @@
"TARGET_ARM || (TARGET_THUMB2 && CONST_INT_P (operands[2]))"
"bics%?\\t%4, %3, %1%S0"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "conds" "set")
(set_attr "shift" "1")
(set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
@@ -3218,7 +3193,6 @@
#"
[(set_attr "length" "4,8")
(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "logic_reg,multiple")]
)
@@ -3412,7 +3386,6 @@
#"
[(set_attr "length" "4,8")
(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "logic_reg")]
)
@@ -3556,7 +3529,6 @@
[(set_attr "length" "8")
(set_attr "ce_count" "2")
(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "multiple")]
)
@@ -3694,7 +3666,6 @@
"TARGET_32BIT"
"bic%?\\t%0, %1, %1, asr #31"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "logic_shift_reg")]
)
@@ -3705,7 +3676,6 @@
"TARGET_32BIT"
"orr%?\\t%0, %1, %1, asr #31"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "logic_shift_reg")]
)
@@ -3756,7 +3726,6 @@
"TARGET_32BIT"
"and%?\\t%0, %1, %1, asr #31"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "logic_shift_reg")]
)
@@ -3993,7 +3962,6 @@
return "usat%?\t%0, %1, %3";
}
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "alus_imm")]
)
@@ -4020,7 +3988,6 @@
return "usat%?\t%0, %1, %4%S3";
}
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "shift" "3")
(set_attr "type" "logic_shift_reg")])
@@ -4233,7 +4200,6 @@
"TARGET_32BIT"
"mvn%?\\t%0, %1%S3"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "shift" "1")
(set_attr "arch" "32,a")
(set_attr "type" "mvn_shift,mvn_shift_reg")])
@@ -4509,7 +4475,6 @@
"sbfx%?\t%0, %1, %3, %2"
[(set_attr "length" "4")
(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "bfm")]
)
@@ -4524,7 +4489,6 @@
"ubfx%?\t%0, %1, %3, %2"
[(set_attr "length" "4")
(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "bfm")]
)
@@ -4540,7 +4504,6 @@
sdiv\t%0, %1, %2"
[(set_attr "arch" "32,v8mb")
(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "sdiv")]
)
@@ -4554,7 +4517,6 @@
udiv\t%0, %1, %2"
[(set_attr "arch" "32,v8mb")
(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "udiv")]
)
@@ -5338,8 +5300,7 @@
"TARGET_INT_SIMD"
"uxtah%?\\t%0, %2, %1"
[(set_attr "type" "alu_shift_reg")
- (set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")]
+ (set_attr "predicable" "yes")]
)
(define_expand "zero_extendqisi2"
@@ -5409,7 +5370,6 @@
"TARGET_INT_SIMD"
"uxtab%?\\t%0, %2, %1"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "alu_shift_reg")]
)
@@ -5462,7 +5422,6 @@
"tst%?\\t%0, #255"
[(set_attr "conds" "set")
(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "logic_imm")]
)
@@ -5572,8 +5531,7 @@
sxth%?\\t%0, %1
ldrsh%?\\t%0, %1"
[(set_attr "type" "extend,load_byte")
- (set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")]
+ (set_attr "predicable" "yes")]
)
(define_insn "*arm_extendhisi2addsi"
@@ -5677,8 +5635,7 @@
"TARGET_INT_SIMD"
"sxtab%?\\t%0, %2, %1"
[(set_attr "type" "alu_shift_reg")
- (set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")]
+ (set_attr "predicable" "yes")]
)
(define_expand "extendsfdf2"
@@ -6045,7 +6002,6 @@
movt\t%0, #:upper16:%c2"
[(set_attr "arch" "32,v8mb")
(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "length" "4")
(set_attr "type" "alu_sreg")]
)
@@ -6925,8 +6881,7 @@
[(set_attr "conds" "unconditional")
(set_attr "type" "load_4,store_4,mov_reg,multiple")
(set_attr "length" "4,4,4,8")
- (set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")]
+ (set_attr "predicable" "yes")]
)
(define_expand "movsf"
@@ -6979,7 +6934,6 @@
ldr%?\\t%0, %1\\t%@ float
str%?\\t%1, %0\\t%@ float"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "mov_reg,load_4,store_4")
(set_attr "arm_pool_range" "*,4096,*")
(set_attr "thumb2_pool_range" "*,4094,*")
@@ -7402,7 +7356,7 @@
operands[1] = gen_lowpart (SImode, operands[1]);
}
[(set_attr "conds" "set")
- (set_attr "enabled_for_depr_it" "yes,yes,no,*")
+ (set_attr "enabled_for_short_it" "yes,yes,no,*")
(set_attr "arch" "t2,t2,t2,a")
(set_attr "length" "6,6,10,8")
(set_attr "type" "multiple")]
@@ -8789,7 +8743,6 @@
"TARGET_32BIT"
"<arith_shift_insn>%?\\t%0, %1, %2, lsl %b3"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "shift" "2")
(set_attr "arch" "a,t2")
(set_attr "type" "alu_shift_imm")])
@@ -8804,7 +8757,6 @@
"TARGET_32BIT && GET_CODE (operands[2]) != MULT"
"<arith_shift_insn>%?\\t%0, %1, %3%S2"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "shift" "3")
(set_attr "arch" "a,t2,a")
(set_attr "type" "alu_shift_imm,alu_shift_imm,alu_shift_reg")])
@@ -9475,7 +9427,7 @@
[(set_attr "conds" "set")
(set_attr "predicable" "no")
(set_attr "arch" "t2,t2,t2,t2,t2,any,any,any,any")
- (set_attr "enabled_for_depr_it" "yes,no,no,no,no,no,no,no,no")
+ (set_attr "enabled_for_short_it" "yes,no,no,no,no,no,no,no,no")
(set_attr_alternative "length"
[(const_int 6)
(const_int 8)
@@ -9558,7 +9510,7 @@
"
[(set_attr "conds" "set")
(set_attr "arch" "t2,t2,t2,t2,t2,any,any,any,any")
- (set_attr "enabled_for_depr_it" "yes,no,no,no,no,no,no,no,no")
+ (set_attr "enabled_for_short_it" "yes,no,no,no,no,no,no,no,no")
(set_attr_alternative "length"
[(const_int 6)
(const_int 8)
@@ -9606,7 +9558,7 @@
DOM_CC_X_OR_Y),
CC_REGNUM);"
[(set_attr "conds" "clob")
- (set_attr "enabled_for_depr_it" "yes,no")
+ (set_attr "enabled_for_short_it" "yes,no")
(set_attr "length" "16")
(set_attr "type" "multiple")]
)
@@ -9637,7 +9589,7 @@
(set (match_dup 7) (ne:SI (match_dup 0) (const_int 0)))]
""
[(set_attr "conds" "set")
- (set_attr "enabled_for_depr_it" "yes,no")
+ (set_attr "enabled_for_short_it" "yes,no")
(set_attr "length" "16")
(set_attr "type" "multiple")]
)
@@ -9670,7 +9622,7 @@
DOM_CC_X_AND_Y),
CC_REGNUM);"
[(set_attr "conds" "clob")
- (set_attr "enabled_for_depr_it" "yes,no")
+ (set_attr "enabled_for_short_it" "yes,no")
(set_attr "length" "16")
(set_attr "type" "multiple")]
)
@@ -9701,7 +9653,7 @@
(set (match_dup 7) (ne:SI (match_dup 0) (const_int 0)))]
""
[(set_attr "conds" "set")
- (set_attr "enabled_for_depr_it" "yes,no")
+ (set_attr "enabled_for_short_it" "yes,no")
(set_attr "length" "16")
(set_attr "type" "multiple")]
)
@@ -9888,7 +9840,7 @@
}
"
[(set_attr "conds" "clob")
- (set_attr "enabled_for_depr_it" "no,yes,yes")
+ (set_attr "enabled_for_short_it" "no,yes,yes")
(set_attr "type" "multiple")]
)
@@ -10506,7 +10458,7 @@
[(set_attr "conds" "use")
(set_attr "length" "4")
(set_attr "arch" "t2,32")
- (set_attr "enabled_for_depr_it" "yes,no")
+ (set_attr "enabled_for_short_it" "yes,no")
(set_attr "type" "logic_shift_imm")]
)
@@ -10552,7 +10504,7 @@
[(set_attr "conds" "use")
(set_attr "length" "4")
(set_attr "arch" "t2,32")
- (set_attr "enabled_for_depr_it" "yes,no")
+ (set_attr "enabled_for_short_it" "yes,no")
(set_attr "type" "logic_shift_imm")]
)
@@ -11288,7 +11240,6 @@
"TARGET_32BIT && arm_arch5"
"clz%?\\t%0, %1"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "clz")])
(define_insn "rbitsi2"
@@ -11297,7 +11248,6 @@
"TARGET_32BIT && arm_arch_thumb2"
"rbit%?\\t%0, %1"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "clz")])
;; Keep this as a CTZ expression until after reload and then split
@@ -11449,7 +11399,6 @@
movt\t%0, %L1"
[(set_attr "arch" "32,v8mb")
(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "length" "4")
(set_attr "type" "alu_sreg")]
)
@@ -11465,7 +11414,6 @@
[(set_attr "arch" "t1,t2,32")
(set_attr "length" "2,2,4")
(set_attr "predicable" "no,yes,yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "rev")]
)
@@ -11713,8 +11661,7 @@
false, true))"
"ldrd%?\t%0, %3, [%1, %2]"
[(set_attr "type" "load_8")
- (set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")])
+ (set_attr "predicable" "yes")])
(define_insn "*thumb2_ldrd_base"
[(set (match_operand:SI 0 "s_register_operand" "=r")
@@ -11727,8 +11674,7 @@
operands[1], 0, false, true))"
"ldrd%?\t%0, %2, [%1]"
[(set_attr "type" "load_8")
- (set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")])
+ (set_attr "predicable" "yes")])
(define_insn "*thumb2_ldrd_base_neg"
[(set (match_operand:SI 0 "s_register_operand" "=r")
@@ -11741,8 +11687,7 @@
operands[1], -4, false, true))"
"ldrd%?\t%0, %2, [%1, #-4]"
[(set_attr "type" "load_8")
- (set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")])
+ (set_attr "predicable" "yes")])
(define_insn "*thumb2_strd"
[(set (mem:SI (plus:SI (match_operand:SI 0 "s_register_operand" "rk")
@@ -11758,8 +11703,7 @@
false, false))"
"strd%?\t%2, %4, [%0, %1]"
[(set_attr "type" "store_8")
- (set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")])
+ (set_attr "predicable" "yes")])
(define_insn "*thumb2_strd_base"
[(set (mem:SI (match_operand:SI 0 "s_register_operand" "rk"))
@@ -11772,8 +11716,7 @@
operands[0], 0, false, false))"
"strd%?\t%1, %2, [%0]"
[(set_attr "type" "store_8")
- (set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")])
+ (set_attr "predicable" "yes")])
(define_insn "*thumb2_strd_base_neg"
[(set (mem:SI (plus:SI (match_operand:SI 0 "s_register_operand" "rk")
@@ -11786,8 +11729,7 @@
operands[0], -4, false, false))"
"strd%?\t%1, %2, [%0, #-4]"
[(set_attr "type" "store_8")
- (set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")])
+ (set_attr "predicable" "yes")])
;; ARMv8 CRC32 instructions.
(define_insn "<crc_variant>"
diff --git a/gcc/config/arm/ldmstm.md b/gcc/config/arm/ldmstm.md
index 01fbb553fbc89831fb44248cafd289a8d1a74089..d7650d4f809897e4f5f638690dfa7fd7cb8e33aa 100644
--- a/gcc/config/arm/ldmstm.md
+++ b/gcc/config/arm/ldmstm.md
@@ -37,8 +37,7 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
"ldm%?\t%5, {%1, %2, %3, %4}"
[(set_attr "type" "load_16")
- (set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")])
+ (set_attr "predicable" "yes")])
(define_insn "*thumb_ldm4_ia"
[(match_parallel 0 "load_multiple_operation"
@@ -75,8 +74,7 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 5"
"ldmia%?\t%5!, {%1, %2, %3, %4}"
[(set_attr "type" "load_16")
- (set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")])
+ (set_attr "predicable" "yes")])
(define_insn "*thumb_ldm4_ia_update"
[(match_parallel 0 "load_multiple_operation"
@@ -110,8 +108,7 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
"stm%?\t%5, {%1, %2, %3, %4}"
[(set_attr "type" "store_16")
- (set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")])
+ (set_attr "predicable" "yes")])
(define_insn "*stm4_ia_update"
[(match_parallel 0 "store_multiple_operation"
@@ -128,8 +125,7 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 5"
"stmia%?\t%5!, {%1, %2, %3, %4}"
[(set_attr "type" "store_16")
- (set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")])
+ (set_attr "predicable" "yes")])
(define_insn "*thumb_stm4_ia_update"
[(match_parallel 0 "store_multiple_operation"
@@ -306,8 +302,7 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
"ldmdb%?\t%5, {%1, %2, %3, %4}"
[(set_attr "type" "load_16")
- (set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")])
+ (set_attr "predicable" "yes")])
(define_insn "*ldm4_db_update"
[(match_parallel 0 "load_multiple_operation"
@@ -328,8 +323,7 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 5"
"ldmdb%?\t%5!, {%1, %2, %3, %4}"
[(set_attr "type" "load_16")
- (set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")])
+ (set_attr "predicable" "yes")])
(define_insn "*stm4_db"
[(match_parallel 0 "store_multiple_operation"
@@ -344,8 +338,7 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
"stmdb%?\t%5, {%1, %2, %3, %4}"
[(set_attr "type" "store_16")
- (set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")])
+ (set_attr "predicable" "yes")])
(define_insn "*stm4_db_update"
[(match_parallel 0 "store_multiple_operation"
@@ -362,8 +355,7 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 5"
"stmdb%?\t%5!, {%1, %2, %3, %4}"
[(set_attr "type" "store_16")
- (set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")])
+ (set_attr "predicable" "yes")])
(define_peephole2
[(set (match_operand:SI 0 "s_register_operand" "")
@@ -485,8 +477,7 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
"ldm%?\t%4, {%1, %2, %3}"
[(set_attr "type" "load_12")
- (set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")])
+ (set_attr "predicable" "yes")])
(define_insn "*thumb_ldm3_ia"
[(match_parallel 0 "load_multiple_operation"
@@ -517,8 +508,7 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
"ldmia%?\t%4!, {%1, %2, %3}"
[(set_attr "type" "load_12")
- (set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")])
+ (set_attr "predicable" "yes")])
(define_insn "*thumb_ldm3_ia_update"
[(match_parallel 0 "load_multiple_operation"
@@ -547,8 +537,7 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
"stm%?\t%4, {%1, %2, %3}"
[(set_attr "type" "store_12")
- (set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")])
+ (set_attr "predicable" "yes")])
(define_insn "*stm3_ia_update"
[(match_parallel 0 "store_multiple_operation"
@@ -563,8 +552,7 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
"stmia%?\t%4!, {%1, %2, %3}"
[(set_attr "type" "store_12")
- (set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")])
+ (set_attr "predicable" "yes")])
(define_insn "*thumb_stm3_ia_update"
[(match_parallel 0 "store_multiple_operation"
@@ -716,8 +704,7 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
"ldmdb%?\t%4, {%1, %2, %3}"
[(set_attr "type" "load_12")
- (set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")])
+ (set_attr "predicable" "yes")])
(define_insn "*ldm3_db_update"
[(match_parallel 0 "load_multiple_operation"
@@ -735,8 +722,7 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
"ldmdb%?\t%4!, {%1, %2, %3}"
[(set_attr "type" "load_12")
- (set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")])
+ (set_attr "predicable" "yes")])
(define_insn "*stm3_db"
[(match_parallel 0 "store_multiple_operation"
@@ -749,8 +735,7 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
"stmdb%?\t%4, {%1, %2, %3}"
[(set_attr "type" "store_12")
- (set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")])
+ (set_attr "predicable" "yes")])
(define_insn "*stm3_db_update"
[(match_parallel 0 "store_multiple_operation"
@@ -765,8 +750,7 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 4"
"stmdb%?\t%4!, {%1, %2, %3}"
[(set_attr "type" "store_12")
- (set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")])
+ (set_attr "predicable" "yes")])
(define_peephole2
[(set (match_operand:SI 0 "s_register_operand" "")
@@ -871,8 +855,7 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 2"
"ldm%?\t%3, {%1, %2}"
[(set_attr "type" "load_8")
- (set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")])
+ (set_attr "predicable" "yes")])
(define_insn "*thumb_ldm2_ia"
[(match_parallel 0 "load_multiple_operation"
@@ -897,8 +880,7 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
"ldmia%?\t%3!, {%1, %2}"
[(set_attr "type" "load_8")
- (set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")])
+ (set_attr "predicable" "yes")])
(define_insn "*thumb_ldm2_ia_update"
[(match_parallel 0 "load_multiple_operation"
@@ -922,8 +904,7 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 2"
"stm%?\t%3, {%1, %2}"
[(set_attr "type" "store_8")
- (set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")])
+ (set_attr "predicable" "yes")])
(define_insn "*stm2_ia_update"
[(match_parallel 0 "store_multiple_operation"
@@ -936,8 +917,7 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
"stmia%?\t%3!, {%1, %2}"
[(set_attr "type" "store_8")
- (set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")])
+ (set_attr "predicable" "yes")])
(define_insn "*thumb_stm2_ia_update"
[(match_parallel 0 "store_multiple_operation"
@@ -1064,8 +1044,7 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 2"
"ldmdb%?\t%3, {%1, %2}"
[(set_attr "type" "load_8")
- (set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")])
+ (set_attr "predicable" "yes")])
(define_insn "*ldm2_db_update"
[(match_parallel 0 "load_multiple_operation"
@@ -1080,8 +1059,7 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
"ldmdb%?\t%3!, {%1, %2}"
[(set_attr "type" "load_8")
- (set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")])
+ (set_attr "predicable" "yes")])
(define_insn "*stm2_db"
[(match_parallel 0 "store_multiple_operation"
@@ -1092,8 +1070,7 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 2"
"stmdb%?\t%3, {%1, %2}"
[(set_attr "type" "store_8")
- (set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")])
+ (set_attr "predicable" "yes")])
(define_insn "*stm2_db_update"
[(match_parallel 0 "store_multiple_operation"
@@ -1106,8 +1083,7 @@
"TARGET_32BIT && XVECLEN (operands[0], 0) == 3"
"stmdb%?\t%3!, {%1, %2}"
[(set_attr "type" "store_8")
- (set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")])
+ (set_attr "predicable" "yes")])
(define_peephole2
[(set (match_operand:SI 0 "s_register_operand" "")
diff --git a/gcc/config/arm/sync.md b/gcc/config/arm/sync.md
index b4b4f2e6815e7c31c9874c19af31e908107e6a62..37a4cb3f1c53021114843417022c8d0adb4801de 100644
--- a/gcc/config/arm/sync.md
+++ b/gcc/config/arm/sync.md
@@ -87,8 +87,7 @@
}
}
[(set_attr "arch" "32,v8mb,any")
- (set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")])
+ (set_attr "predicable" "yes")])
(define_insn "atomic_store<mode>"
[(set (match_operand:QHSI 0 "memory_operand" "=Q,Q,Q")
@@ -115,8 +114,7 @@
}
}
[(set_attr "arch" "32,v8mb,any")
- (set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")])
+ (set_attr "predicable" "yes")])
;; An LDRD instruction usable by the atomic_loaddi expander on LPAE targets
@@ -127,8 +125,7 @@
VUNSPEC_LDRD_ATOMIC))]
"ARM_DOUBLEWORD_ALIGN && TARGET_HAVE_LPAE"
"ldrd%?\t%0, %H0, %C1"
- [(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")])
+ [(set_attr "predicable" "yes")])
;; There are three ways to expand this depending on the architecture
;; features available. As for the barriers, a load needs a barrier
@@ -461,8 +458,7 @@
ldrex<sync_sfx>%?\t%0, %C1
ldrex<sync_sfx>\t%0, %C1"
[(set_attr "arch" "32,v8mb")
- (set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")])
+ (set_attr "predicable" "yes")])
(define_insn "arm_load_acquire_exclusive<mode>"
[(set (match_operand:SI 0 "s_register_operand" "=r,r")
@@ -475,8 +471,7 @@
ldaex<sync_sfx>%?\\t%0, %C1
ldaex<sync_sfx>\\t%0, %C1"
[(set_attr "arch" "32,v8mb")
- (set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")])
+ (set_attr "predicable" "yes")])
(define_insn "arm_load_exclusivesi"
[(set (match_operand:SI 0 "s_register_operand" "=r,r")
@@ -488,8 +483,7 @@
ldrex%?\t%0, %C1
ldrex\t%0, %C1"
[(set_attr "arch" "32,v8mb")
- (set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")])
+ (set_attr "predicable" "yes")])
(define_insn "arm_load_acquire_exclusivesi"
[(set (match_operand:SI 0 "s_register_operand" "=r,r")
@@ -501,8 +495,7 @@
ldaex%?\t%0, %C1
ldaex\t%0, %C1"
[(set_attr "arch" "32,v8mb")
- (set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")])
+ (set_attr "predicable" "yes")])
(define_insn "arm_load_exclusivedi"
[(set (match_operand:DI 0 "s_register_operand" "=r")
@@ -511,8 +504,7 @@
VUNSPEC_LL))]
"TARGET_HAVE_LDREXD"
"ldrexd%?\t%0, %H0, %C1"
- [(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")])
+ [(set_attr "predicable" "yes")])
(define_insn "arm_load_acquire_exclusivedi"
[(set (match_operand:DI 0 "s_register_operand" "=r")
@@ -521,8 +513,7 @@
VUNSPEC_LAX))]
"TARGET_HAVE_LDACQEXD && ARM_DOUBLEWORD_ALIGN"
"ldaexd%?\t%0, %H0, %C1"
- [(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")])
+ [(set_attr "predicable" "yes")])
(define_insn "arm_store_exclusive<mode>"
[(set (match_operand:SI 0 "s_register_operand" "=&r")
@@ -548,8 +539,7 @@
else
return "strex<sync_sfx>%?\t%0, %2, %C1";
}
- [(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")])
+ [(set_attr "predicable" "yes")])
(define_insn "arm_store_release_exclusivedi"
[(set (match_operand:SI 0 "s_register_operand" "=&r")
@@ -564,8 +554,7 @@
gcc_assert ((REGNO (operands[2]) & 1) == 0 || TARGET_THUMB2);
return "stlexd%?\t%0, %2, %H2, %C1";
}
- [(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")])
+ [(set_attr "predicable" "yes")])
(define_insn "arm_store_release_exclusive<mode>"
[(set (match_operand:SI 0 "s_register_operand" "=&r,&r")
@@ -579,5 +568,4 @@
stlex<sync_sfx>%?\t%0, %2, %C1
stlex<sync_sfx>\t%0, %2, %C1"
[(set_attr "arch" "32,v8mb")
- (set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")])
+ (set_attr "predicable" "yes")])
diff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md
index b2b7c3e12e8b21eb3fcd9b73dbac5f9835dd9aa1..a562488f7c80af8ba5bd5969d597ba80d6195eed 100644
--- a/gcc/config/arm/thumb2.md
+++ b/gcc/config/arm/thumb2.md
@@ -34,7 +34,6 @@
"TARGET_THUMB2"
"bic%?\\t%0, %1, %2%S4"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "shift" "2")
(set_attr "type" "alu_shift_imm")]
)
@@ -57,7 +56,7 @@
(match_dup 2)))]
""
[(set_attr "conds" "clob")
- (set_attr "enabled_for_depr_it" "yes,yes,no")
+ (set_attr "enabled_for_short_it" "yes,yes,no")
(set_attr "length" "6,6,10")
(set_attr "type" "multiple")]
)
@@ -78,7 +77,7 @@
(match_dup 2)))]
""
[(set_attr "conds" "clob")
- (set_attr "enabled_for_depr_it" "yes,yes,no")
+ (set_attr "enabled_for_short_it" "yes,yes,no")
(set_attr "length" "6,6,10")
(set_attr "type" "multiple")]
)
@@ -100,7 +99,7 @@
""
[(set_attr "conds" "clob")
(set_attr "length" "6,6,10")
- (set_attr "enabled_for_depr_it" "yes,yes,no")
+ (set_attr "enabled_for_short_it" "yes,yes,no")
(set_attr "type" "multiple")]
)
@@ -121,7 +120,7 @@
""
[(set_attr "conds" "clob")
(set_attr "length" "6,6,10")
- (set_attr "enabled_for_depr_it" "yes,yes,no")
+ (set_attr "enabled_for_short_it" "yes,yes,no")
(set_attr "type" "multiple")]
)
@@ -172,8 +171,7 @@
[(set_attr "conds" "*,clob,clob")
(set_attr "shift" "1")
(set_attr "predicable" "yes,no,no")
- (set_attr "predicable_short_it" "no")
- (set_attr "enabled_for_depr_it" "yes,yes,no")
+ (set_attr "enabled_for_short_it" "yes,yes,no")
(set_attr "ce_count" "2")
(set_attr "length" "8,6,10")
(set_attr "type" "multiple")]
@@ -226,8 +224,7 @@
[(set_attr "conds" "*,clob,clob")
(set_attr "shift" "1")
(set_attr "predicable" "yes,no,no")
- (set_attr "enabled_for_depr_it" "yes,yes,no")
- (set_attr "predicable_short_it" "no")
+ (set_attr "enabled_for_short_it" "yes,yes,no")
(set_attr "ce_count" "2")
(set_attr "length" "8,6,10")
(set_attr "type" "multiple")]
@@ -354,7 +351,7 @@
(const_int 0)))]
""
[(set_attr "conds" "use")
- (set_attr "enabled_for_depr_it" "yes,no")
+ (set_attr "enabled_for_short_it" "yes,no")
(set_attr "length" "8,10")
(set_attr "type" "multiple")]
)
@@ -504,7 +501,7 @@
DONE;
}
[(set_attr "length" "4,4,6,6,6,6,10,8,10,10,10,6")
- (set_attr "enabled_for_depr_it" "yes,yes,no,no,no,no,no,no,no,no,no,yes")
+ (set_attr "enabled_for_short_it" "yes,yes,no,no,no,no,no,no,no,no,no,yes")
(set_attr "conds" "use")
(set_attr_alternative "type"
[(if_then_else (match_operand 2 "const_int_operand" "")
@@ -1044,7 +1041,6 @@
ldrsb%?\\t%0, %1"
[(set_attr "type" "extend,load_byte")
(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "pool_range" "*,4094")
(set_attr "neg_pool_range" "*,250")]
)
@@ -1058,7 +1054,6 @@
ldrh%?\\t%0, %1"
[(set_attr "type" "extend,load_byte")
(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "pool_range" "*,4094")
(set_attr "neg_pool_range" "*,250")]
)
@@ -1072,7 +1067,6 @@
ldrb%?\\t%0, %1\\t%@ zero_extendqisi2"
[(set_attr "type" "extend,load_byte")
(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "pool_range" "*,4094")
(set_attr "neg_pool_range" "*,250")]
)
@@ -1441,7 +1435,6 @@
"TARGET_THUMB2"
"orn%?\\t%0, %1, %2"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "logic_reg")]
)
@@ -1454,7 +1447,6 @@
"TARGET_THUMB2"
"orn%?\\t%0, %1, %2%S4"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "shift" "2")
(set_attr "type" "alu_shift_imm")]
)
diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md
index a541413c263285870f74c4b22605f32e5b4245e6..075a938d22e40d92aa53e22f622445d4acc14a05 100644
--- a/gcc/config/arm/vfp.md
+++ b/gcc/config/arm/vfp.md
@@ -612,7 +612,6 @@
}
"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type"
"f_mcr,f_mrc,fconsts,f_loads,f_stores,load_4,store_4,fmov,mov_reg")
(set_attr "pool_range" "*,*,*,1018,*,4090,*,*,*")
@@ -824,7 +823,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT"
"vabs%?.f32\\t%0, %1"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "ffariths")]
)
@@ -834,7 +832,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"vabs%?.f64\\t%P0, %P1"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "ffarithd")]
)
@@ -846,7 +843,6 @@
vneg%?.f32\\t%0, %1
eor%?\\t%0, %1, #-2147483648"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "ffariths")]
)
@@ -892,7 +888,6 @@
}
"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "length" "4,4,8")
(set_attr "type" "ffarithd")]
)
@@ -961,7 +956,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT"
"vadd%?.f32\\t%0, %1, %2"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "fadds")]
)
@@ -972,7 +966,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"vadd%?.f64\\t%P0, %P1, %P2"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "faddd")]
)
@@ -995,7 +988,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT"
"vsub%?.f32\\t%0, %1, %2"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "fadds")]
)
@@ -1006,7 +998,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"vsub%?.f64\\t%P0, %P1, %P2"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "faddd")]
)
@@ -1036,7 +1027,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT"
"vdiv%?.f32\\t%0, %1, %2"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "arch" "*,armv6_or_vfpv3")
(set_attr "type" "fdivs")]
)
@@ -1048,7 +1038,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"vdiv%?.f64\\t%P0, %P1, %P2"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "arch" "*,armv6_or_vfpv3")
(set_attr "type" "fdivd")]
)
@@ -1074,7 +1063,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT"
"vmul%?.f32\\t%0, %1, %2"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "fmuls")]
)
@@ -1085,7 +1073,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"vmul%?.f64\\t%P0, %P1, %P2"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "fmuld")]
)
@@ -1116,7 +1103,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && !flag_rounding_math"
"vnmul%?.f32\\t%0, %1, %2"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "fmuls")]
)
@@ -1127,7 +1113,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT"
"vnmul%?.f32\\t%0, %1, %2"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "fmuls")]
)
@@ -1139,7 +1124,6 @@
&& !flag_rounding_math"
"vnmul%?.f64\\t%P0, %P1, %P2"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "fmuld")]
)
@@ -1150,7 +1134,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"vnmul%?.f64\\t%P0, %P1, %P2"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "fmuld")]
)
@@ -1178,7 +1161,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT"
"vmla%?.f32\\t%0, %2, %3"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "fmacs")]
)
@@ -1190,7 +1172,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"vmla%?.f64\\t%P0, %P2, %P3"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "fmacd")]
)
@@ -1214,7 +1195,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT"
"vnmls%?.f32\\t%0, %2, %3"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "fmacs")]
)
@@ -1226,7 +1206,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"vnmls%?.f64\\t%P0, %P2, %P3"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "fmacd")]
)
@@ -1250,7 +1229,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT"
"vmls%?.f32\\t%0, %2, %3"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "fmacs")]
)
@@ -1262,7 +1240,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"vmls%?.f64\\t%P0, %P2, %P3"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "fmacd")]
)
@@ -1289,7 +1266,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT"
"vnmla%?.f32\\t%0, %2, %3"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "fmacs")]
)
@@ -1302,7 +1278,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"vnmla%?.f64\\t%P0, %P2, %P3"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "fmacd")]
)
@@ -1340,7 +1315,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA"
"vfma%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "ffma<vfp_type>")]
)
@@ -1377,7 +1351,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA"
"vfms%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "ffma<vfp_type>")]
)
@@ -1400,7 +1373,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA"
"vfnms%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "ffma<vfp_type>")]
)
@@ -1424,7 +1396,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA"
"vfnma%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "ffma<vfp_type>")]
)
@@ -1437,7 +1408,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"vcvt%?.f64.f32\\t%P0, %1"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvt")]
)
@@ -1447,7 +1417,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"vcvt%?.f32.f64\\t%0, %P1"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvt")]
)
@@ -1457,7 +1426,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FP16 || TARGET_VFP_FP16INST)"
"vcvtb%?.f32.f16\\t%0, %1"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvt")]
)
@@ -1467,7 +1435,6 @@
"TARGET_32BIT && TARGET_FP16_TO_DOUBLE"
"vcvtb%?.f16.f64\\t%0, %P1"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvt")]
)
@@ -1477,7 +1444,6 @@
"TARGET_32BIT && TARGET_FP16_TO_DOUBLE"
"vcvtb%?.f64.f16\\t%P0, %1"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvt")]
)
@@ -1487,7 +1453,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FP16 || TARGET_VFP_FP16INST)"
"vcvtb%?.f16.f32\\t%0, %1"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvt")]
)
@@ -1497,7 +1462,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT"
"vcvt%?.s32.f32\\t%0, %1"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvtf2i")]
)
@@ -1507,7 +1471,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"vcvt%?.s32.f64\\t%0, %P1"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvtf2i")]
)
@@ -1518,7 +1481,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT"
"vcvt%?.u32.f32\\t%0, %1"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvtf2i")]
)
@@ -1528,7 +1490,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"vcvt%?.u32.f64\\t%0, %P1"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvtf2i")]
)
@@ -1539,7 +1500,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT"
"vcvt%?.f32.s32\\t%0, %1"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvti2f")]
)
@@ -1549,7 +1509,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"vcvt%?.f64.s32\\t%P0, %1"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvti2f")]
)
@@ -1560,7 +1519,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT"
"vcvt%?.f32.u32\\t%0, %1"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvti2f")]
)
@@ -1570,7 +1528,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"vcvt%?.f64.u32\\t%P0, %1"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvti2f")]
)
@@ -1607,7 +1564,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT"
"vsqrt%?.f32\\t%0, %1"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "arch" "*,armv6_or_vfpv3")
(set_attr "type" "fsqrts")]
)
@@ -1618,7 +1574,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"vsqrt%?.f64\\t%P0, %P1"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "arch" "*,armv6_or_vfpv3")
(set_attr "type" "fsqrtd")]
)
@@ -1710,7 +1665,6 @@
vcmp%?.f32\\t%0, %1
vcmp%?.f32\\t%0, #0"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "fcmps")]
)
@@ -1723,7 +1677,6 @@
vcmpe%?.f32\\t%0, %1
vcmpe%?.f32\\t%0, #0"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "fcmps")]
)
@@ -1736,7 +1689,6 @@
vcmp%?.f64\\t%P0, %P1
vcmp%?.f64\\t%P0, #0"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "fcmpd")]
)
@@ -1749,7 +1701,6 @@
vcmpe%?.f64\\t%P0, %P1
vcmpe%?.f64\\t%P0, #0"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "fcmpd")]
)
@@ -1762,7 +1713,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP3 && !flag_rounding_math"
"vcvt%?.f32.<FCVTI32typename>\\t%0, %1, %v2"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvti2f")]
)
@@ -1781,7 +1731,6 @@
vmov%?.f64\\t%P0, %1, %1\;vcvt%?.f64.<FCVTI32typename>\\t%P0, %P0, %v2"
[(set_attr "predicable" "yes")
(set_attr "ce_count" "2")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvti2f")
(set_attr "length" "8")]
)
@@ -1794,7 +1743,6 @@
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP3 && !flag_rounding_math"
"vcvt%?.s32.f32\\t%0, %1, %v2"
[(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "f_cvtf2i")]
)
@@ -1940,7 +1888,6 @@
"TARGET_HARD_FLOAT && TARGET_VFP5 <vfp_double_cond>"
"vrint<vrint_variant>%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1"
[(set_attr "predicable" "<vrint_predicable>")
- (set_attr "predicable_short_it" "no")
(set_attr "type" "f_rint<vfp_type>")
(set_attr "conds" "<vrint_conds>")]
)
@@ -1953,8 +1900,7 @@
"register_operand" "<F_constraint>")] VCVT)))]
"TARGET_HARD_FLOAT && TARGET_VFP5 <vfp_double_cond>"
"vcvt<vrint_variant>.<su>32.<V_if_elem>\\t%0, %<V_reg>1"
- [(set_attr "predicable" "no")
- (set_attr "conds" "unconditional")
+ [(set_attr "conds" "unconditional")
(set_attr "type" "f_cvtf2i")]
)