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Hello! Attached patch implements generation of btr, bts and btc instructions. These insns are generated for operations with registers and exact log2 immediates, where bitpos <= 63 and >= 31. Immediates with bits >= 31 are out of range for x86 andq/orq/xorq instructions, so we save a movabsq constant load. 2017-08-14 Uros Bizjak <ubizjak@gmail.com> PR target/46091 * config/i386/i386.md (*anddi_1_btr): New insn_and_split pattern. (*iordi_1_bts): Ditto. (*xordi_1_btc): Ditto. testsuite/ChangeLog: 2017-08-14 Uros Bizjak <ubizjak@gmail.com> PR target/46091 * gcc.target/i386/pr46091-1.c: New test. * gcc.target/i386/pr46091-2.c: Ditto. * gcc.target/i386/pr46091-3.c: Ditto. Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}. Committed to mainline. Uros.
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