This is the mail archive of the gcc-patches@gcc.gnu.org mailing list for the GCC project.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

Re: [PATCH] i386: Set priority to P_AES for Westmere


On Mon, Aug 7, 2017 at 3:26 AM, H.J. Lu <hjl.tools@gmail.com> wrote:
> The difference between Nehalem and Westmere is AES.  We should set
> priority to P_AES for Westmere, not P_PROC_SSE4_2 which is for Nehalem.
> Otherwise, we will pick Nehalem implementation on Westmere.  Tested on
> Westmere.
>
> OK for trunk?
>
> H.J.
> ---
>         PR target/81743
>         * config/i386/i386.c (get_builtin_code_for_version): Set priority
>         to P_AES for Westmere.

OK.

Thanks,
Uros.

>  gcc/config/i386/i386.c | 17 +++++++++++------
>  1 file changed, 11 insertions(+), 6 deletions(-)
>
> diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
> index a5984659eb2..c0b6015991d 100644
> --- a/gcc/config/i386/i386.c
> +++ b/gcc/config/i386/i386.c
> @@ -33417,13 +33417,18 @@ get_builtin_code_for_version (tree decl, tree *predicate_list)
>               break;
>             case PROCESSOR_NEHALEM:
>               if (new_target->x_ix86_isa_flags & OPTION_MASK_ISA_AES)
> -               arg_str = "westmere";
> +               {
> +                 arg_str = "westmere";
> +                 priority = P_AES;
> +               }
>               else
> -               /* We translate "arch=corei7" and "arch=nehalem" to
> -                  "corei7" so that it will be mapped to M_INTEL_COREI7
> -                  as cpu type to cover all M_INTEL_COREI7_XXXs.  */
> -               arg_str = "corei7";
> -             priority = P_PROC_SSE4_2;
> +               {
> +                 /* We translate "arch=corei7" and "arch=nehalem" to
> +                    "corei7" so that it will be mapped to M_INTEL_COREI7
> +                    as cpu type to cover all M_INTEL_COREI7_XXXs.  */
> +                 arg_str = "corei7";
> +                 priority = P_PROC_SSE4_2;
> +               }
>               break;
>             case PROCESSOR_SANDYBRIDGE:
>               if (new_target->x_ix86_isa_flags & OPTION_MASK_ISA_F16C)
> --
> 2.13.3
>


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]