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This patches optimizes the PowerPC vector set operation for 64-bit doubles and longs where the elements in the vector set may have been extracted from another vector (PR target/81593): Here an an example: vector double test_vpasted (vector double high, vector double low) { vector double res; res[1] = high[1]; res[0] = low[0]; return res; } Previously it would generate: xxpermdi 12,34,34,2 vspltisw 2,0 xxlor 0,35,35 xxpermdi 34,34,12,0 xxpermdi 34,0,34,1 and with these patches, it now generates: xxpermdi 34,35,34,1 I have tested it on a little endian power8 system and a big endian power7 system with the usual bootstrap and make checks with no regressions. Can I check this into the trunk? I also built Spec 2006 with the compiler, and saw no changes in the code generated. This isn't surprising because it isn't something that auto vectorization might generate by default. [gcc] 2017-07-27 Michael Meissner <meissner@linux.vnet.ibm.com> PR target/81593 * config/rs6000/rs6000-protos.h (rs6000_emit_xxpermdi): New declaration. * config/rs6000/rs6000.c (rs6000_emit_xxpermdi): New function to emit XXPERMDI accessing either double word in either vector register inputs. * config/rs6000/vsx.md (vsx_concat_<mode>, VSX_D iterator): Rewrite VEC_CONCAT insn to call rs6000_emit_xxpermdi. Simplify the constraints with the removal of the -mupper-regs-* switches. (vsx_concat_<mode>_1): New combiner insns to optimize CONCATs where either register might have come from VEC_SELECT. (vsx_concat_<mode>_2): Likewise. (vsx_concat_<mode>_3): Likewise. (vsx_set_<mode>, VSX_D iterator): Rewrite insn to generate a VEC_CONCAT rather than use an UNSPEC to specify the option. [gcc/testsuite] 2017-07-27 Michael Meissner <meissner@linux.vnet.ibm.com> PR target/81593 * gcc.target/powerpc/vsx-extract-6.c: New test. * gcc.target/powerpc/vsx-extract-7.c: Likewise. -- Michael Meissner, IBM IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA email: meissner@linux.vnet.ibm.com, phone: +1 (978) 899-4797
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