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[PATCH V2 3/7] sparc: introduce insn subtypes
- From: "Jose E. Marchesi" <jose dot marchesi at oracle dot com>
- To: gcc-patches at gcc dot gnu dot org
- Date: Wed, 5 Jul 2017 16:15:22 +0200
- Subject: [PATCH V2 3/7] sparc: introduce insn subtypes
- Authentication-results: sourceware.org; auth=none
- References: <1499264126-31635-1-git-send-email-jose.marchesi@oracle.com>
This patch introduces a new insn attribute `subtype', and marks
existing insns appropriately. The resulting instruction hierarchy is
documented in a comment.
gcc/ChangeLog:
* config/sparc/sparc.md ("subtype"): New insn attribute.
("*wrgsr_sp64"): Set insn subtype.
("*rdgsr_sp64"): Likewise.
("alignaddrsi_vis"): Likewise.
("alignaddrdi_vis"): Likewise.
("alignaddrlsi_vis"): Likewise.
("alignaddrldi_vis"): Likewise.
("<plusminus_insn><VADDSUB:mode>3"): Likewise.
("fexpand_vis"): Likewise.
("fpmerge_vis"): Likewise.
("faligndata<VM64:mode>_vis"): Likewise.
("bshuffle<VM64:mode>_vis"): Likewise.
("cmask8<P:mode>_vis"): Likewise.
("cmask16<P:mode>_vis"): Likewise.
("cmask32<P:mode>_vis"): Likewise.
("fchksm16_vis"): Likewise.
("v<vis3_shift_patname><GCM:mode>3"): Likewise.
("fmean16_vis"): Likewise.
("fp<plusminus_insn>64_vis"): Likewise.
("<plusminus_insn>v8qi3"): Likewise.
("<vis3_addsub_ss_patname><VASS:mode>3"): Likewise.
("<vis4_minmax_patname><VMMAX:mode>3"): Likewise.
("<vis4_uminmax_patname><VMMAX:mode>3"): Likewise.
("<vis3_addsub_ss_patname>v8qi3"): Likewise.
("<vis4_addsub_us_patname><VAUS:mode>3"): Likewise.
("*movqi_insn"): Likewise.
("*movhi_insn"): Likewise.
("*movsi_insn"): Likewise.
("movsi_pic_gotdata_op"): Likewise.
("*movdi_insn_sp32"): Likewise.
("*movdi_insn_sp64"): Likewise.
("movdi_pic_gotdata_op"): Likewise.
("*movsf_insn"): Likewise.
("*movdf_insn_sp32"): Likewise.
("*movdf_insn_sp64"): Likewise.
("*zero_extendhisi2_insn"): Likewise.
("*zero_extendqihi2_insn"): Likewise.
("*zero_extendqisi2_insn"): Likewise.
("*zero_extendqidi2_insn"): Likewise.
("*zero_extendhidi2_insn"): Likewise.
("*zero_extendsidi2_insn_sp64"): Likewise.
("ldfsr"): Likewise.
("prefetch_64"): Likewise.
("prefetch_32"): Likewise.
("tie_ld32"): Likewise.
("tie_ld64"): Likewise.
("*tldo_ldub_sp32"): Likewise.
("*tldo_ldub1_sp32"): Likewise.
("*tldo_ldub2_sp32"): Likewise.
("*tldo_ldub_sp64"): Likewise.
("*tldo_ldub1_sp64"): Likewise.
("*tldo_ldub2_sp64"): Likewise.
("*tldo_ldub3_sp64"): Likewise.
("*tldo_lduh_sp32"): Likewise.
("*tldo_lduh1_sp32"): Likewise.
("*tldo_lduh_sp64"): Likewise.
("*tldo_lduh1_sp64"): Likewise.
("*tldo_lduh2_sp64"): Likewise.
("*tldo_lduw_sp32"): Likewise.
("*tldo_lduw_sp64"): Likewise.
("*tldo_lduw1_sp64"): Likewise.
("*tldo_ldx_sp64"): Likewise.
("*mov<VM32:mode>_insn"): Likewise.
("*mov<VM64:mode>_insn_sp64"): Likewise.
("*mov<VM64:mode>_insn_sp32"): Likewise.
---
gcc/ChangeLog | 68 ++++++++++++++++
gcc/config/sparc/sparc.md | 199 ++++++++++++++++++++++++++++++++++++++++------
2 files changed, 243 insertions(+), 24 deletions(-)
diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md
index 04da8ae..d1bf6a7 100644
--- a/gcc/config/sparc/sparc.md
+++ b/gcc/config/sparc/sparc.md
@@ -268,7 +268,86 @@
(eq_attr "cpu_feature" "vis4") (symbol_ref "TARGET_VIS4")]
(const_int 0)))
-;; Insn type.
+;; The SPARC instructions used by the backend are organized into a
+;; hierarchy using the insn attributes "type" and "subtype".
+;;
+;; The mnemonics used in the list below are the architectural names
+;; used in the Oracle SPARC Architecture specs. A / character
+;; separates the type from the subtype where appropriate. For
+;; brevity, text enclosed in {} denotes alternatives, while text
+;; enclosed in [] is optional.
+;;
+;; Please keep this list updated. It is of great help for keeping the
+;; correctness and coherence of the DFA schedulers.
+;;
+;; ialu: <empty>
+;; ialuX: ADD[X]C SUB[X]C
+;; shift: SLL[X] SRL[X] SRA[X]
+;; cmove: MOV{A,N,NE,E,G,LE,GE,L,GU,LEU,CC,CS,POS,NEG,VC,VS}
+;; MOVF{A,N,U,G,UG,L,UL,LG,NE,E,UE,GE,UGE,LE,ULE,O}
+;; MOVR{Z,LEZ,LZ,NZ,GZ,GEZ}
+;; compare: ADDcc ADDCcc ANDcc ORcc SUBcc SUBCcc XORcc XNORcc
+;; imul: MULX SMUL[cc] UMUL UMULXHI XMULX XMULXHI
+;; idiv: UDIVX SDIVX
+;; flush: FLUSH
+;; load/regular: LD{UB,UH,UW} LDFSR
+;; load/prefetch: PREFETCH
+;; fpload: LDF LDDF LDQF
+;; sload: LD{SB,SH,SW}
+;; store: ST{B,H,W,X} STFSR
+;; fpstore: STF STDF STQF
+;; cbcond: CWB{NE,E,G,LE,GE,L,GU,LEU,CC,CS,POS,NEG,VC,VS}
+;; CXB{NE,E,G,LE,GE,L,GU,LEU,CC,CS,POS,NEG,VC,VS}
+;; uncond_branch: BA BPA JMPL
+;; branch: B{NE,E,G,LE,GE,L,GU,LEU,CC,CS,POS,NEG,VC,VS}
+;; BP{NE,E,G,LE,GE,L,GU,LEU,CC,CS,POS,NEG,VC,VS}
+;; FB{U,G,UG,L,UL,LG,NE,BE,UE,GE,UGE,LE,ULE,O}
+;; call: CALL
+;; return: RESTORE RETURN
+;; fpmove: FABS{s,d,q} FMOV{s,d,q} FNEG{s,d,q}
+;; fpcmove: FMOV{S,D,Q}{icc,xcc,fcc}
+;; fpcrmove: FMOVR{s,d,q}{Z,LEZ,LZ,NZ,GZ,GEZ}
+;; fp: FADD{s,d,q} FSUB{s,d,q} FHSUB{s,d} FNHADD{s,d} FNADD{s,d}
+;; FiTO{s,d,q} FsTO{i,x,d,q} FdTO{i,x,s,q} FxTO{d,s,q} FqTO{i,x,s,d}
+;; fpcmp: FCMP{s,d,q} FCMPE{s,d,q}
+;; fpmul: FMADD{s,d} FMSUB{s,d} FMUL{s,d,q} FNMADD{s,d}
+;; FNMSUB{s,d} FNMUL{s,d} FNsMULd FsMULd
+;; FdMULq
+;; array: ARRAY{8,16,32}
+;; bmask: BMASK
+;; edge: EDGE{8,16,32}[L]cc
+;; edgen: EDGE{8,16,32}[L]n
+;; fpdivs: FDIV{s,q}
+;; fpsqrts: FSQRT{s,q}
+;; fpdivd: FDIVd
+;; fpsqrtd: FSQRTd
+;; lzd: LZCNT
+;; fga/addsub64: FP{ADD,SUB}64
+;; fga/fpu: FCHKSM16 FEXPANd FMEAN16 FPMERGE
+;; FS{LL,RA,RL}{16,32}
+;; fga/maxmin: FP{MAX,MIN}[U]{8,16,32}
+;; fga/cmask: CMASK{8,16,32}
+;; fga/other: BSHUFFLE FALIGNDATAg FP{ADD,SUB}[S]{8,16,32}
+;; FP{ADD,SUB}US{8,16}
+;; gsr/reg: RDGSR WRGSR
+;; gsr/alignaddr: ALIGNADDRESS[_LITTLE]
+;; vismv/double: FSRC2d
+;; vismv/single: MOVwTOs FSRC2s
+;; vismv/movstouw: MOVsTOuw
+;; vismv/movxtod: MOVxTOd
+;; vismv/movdtox: MOVdTOx
+;; visl/single: F{AND,NAND,NOR,OR,NOT1}s
+;; F{AND,OR}NOT{1,2}s
+;; FONEs F{ZERO,XNOR,XOR}s FNOT2s
+;; visl/double: FONEd FZEROd FNOT1d F{OR,AND,XOR}d F{NOR,NAND,XNOR}d
+;; F{OR,AND}NOT1d F{OR,AND}NOT2d
+;; viscmp: FPCMP{LE,GT,NE,EQ}{8,16,32} FPCMPU{LE,GT,NE,EQ}{8,16,32}
+;; fgm_pack: FPACKFIX FPACK{8,16,32}
+;; fgm_mul: FMUL8SUx16 FMUL8ULx16 FMUL8x16 FMUL8x16AL
+;; FMUL8x16AU FMULD8SUx16 FMULD8ULx16
+;; pdist: PDIST
+;; pdistn: PDISTN
+
(define_attr "type"
"ialu,compare,shift,
load,sload,store,
@@ -288,6 +367,13 @@
multi,savew,flushw,iflush,trap,lzd"
(const_string "ialu"))
+(define_attr "subtype"
+ "single,double,movstouw,movxtod,movdtox,
+ addsub64,cmask,fpu,maxmin,other,
+ reg,alignaddr,
+ prefetch,regular"
+ (const_string "single"))
+
;; True if branch/call has empty delay slot and will emit a nop in it
(define_attr "empty_delay_slot" "false,true"
(symbol_ref "(empty_delay_slot (insn)
@@ -1508,6 +1594,7 @@
ldub\t%1, %0
stb\t%r1, %0"
[(set_attr "type" "*,load,store")
+ (set_attr "subtype" "*,regular,*")
(set_attr "us3load_type" "*,3cycle,*")])
(define_expand "movhi"
@@ -1530,6 +1617,7 @@
lduh\t%1, %0
sth\t%r1, %0"
[(set_attr "type" "*,*,load,store")
+ (set_attr "subtype" "*,*,regular,*")
(set_attr "us3load_type" "*,*,3cycle,*")])
;; We always work with constants here.
@@ -1567,6 +1655,7 @@
fzeros\t%0
fones\t%0"
[(set_attr "type" "*,*,load,store,vismv,vismv,fpmove,fpload,fpstore,visl,visl")
+ (set_attr "subtype" "*,*,regular,*,movstouw,single,*,*,*,single,single")
(set_attr "cpu_feature" "*,*,*,*,vis3,vis3,*,*,*,vis,vis")
(set_attr "v3pipe" "*,*,*,*,true,true,*,*,*,true,true")])
@@ -1625,7 +1714,8 @@
return "ld\t[%1 + %2], %0";
#endif
}
- [(set_attr "type" "load")])
+ [(set_attr "type" "load")
+ (set_attr "subtype" "regular")])
(define_expand "movsi_pic_label_ref"
[(set (match_dup 3) (high:SI
@@ -1734,7 +1824,9 @@
std\t%1, %0
fzero\t%0
fone\t%0"
- [(set_attr "type" "store,*,load,store,load,store,*,*,fpload,fpstore,*,*,fpmove,*,*,*,fpload,fpstore,visl,visl")
+ [(set_attr "type" "store,*,load,store,load,store,*,*,fpload,fpstore,*,*,fpmove,*,*,*,fpload,fpstore,visl,
+visl")
+ (set_attr "subtype" "*,*,regular,*,regular,*,*,*,*,*,*,*,*,*,*,*,*,*,double,double")
(set_attr "length" "*,2,*,*,*,*,2,2,*,*,2,2,*,2,2,2,*,*,*,*")
(set_attr "fptype" "*,*,*,*,*,*,*,*,*,*,*,*,double,*,*,*,*,*,double,double")
(set_attr "cpu_feature" "v9,*,*,*,*,*,*,*,fpu,fpu,fpu,fpu,v9,fpunotv9,vis3,vis3,fpu,fpu,vis,vis")
@@ -1760,6 +1852,7 @@
fzero\t%0
fone\t%0"
[(set_attr "type" "*,*,load,store,vismv,vismv,fpmove,fpload,fpstore,visl,visl")
+ (set_attr "subtype" "*,*,regular,*,movdtox,movxtod,*,*,*,double,double")
(set_attr "fptype" "*,*,*,*,*,*,double,*,*,double,double")
(set_attr "cpu_feature" "*,*,*,*,vis3,vis3,*,*,*,vis,vis")
(set_attr "v3pipe" "*,*,*,*,*,*,*,*,*,true,true")])
@@ -1848,7 +1941,8 @@
return "ldx\t[%1 + %2], %0";
#endif
}
- [(set_attr "type" "load")])
+ [(set_attr "type" "load")
+ (set_attr "subtype" "regular")])
(define_insn "*sethi_di_medlow_embmedany_pic"
[(set (match_operand:DI 0 "register_operand" "=r")
@@ -2290,6 +2384,7 @@
}
}
[(set_attr "type" "visl,visl,fpmove,*,*,*,vismv,vismv,fpload,load,fpstore,store")
+ (set_attr "subtype" "single,single,*,*,*,*,movstouw,single,*,regular,*,*")
(set_attr "cpu_feature" "vis,vis,fpu,*,*,*,vis3,vis3,fpu,*,fpu,*")
(set_attr "v3pipe" "true,true,*,*,*,*,true,true,*,*,*,*")])
@@ -2363,6 +2458,7 @@
ldd\t%1, %0
std\t%1, %0"
[(set_attr "type" "store,*,visl,visl,fpmove,*,*,*,fpload,fpstore,load,store,*,*,*,load,store")
+ (set_attr "subtype" "*,*,double,double,*,*,*,*,*,*,regular,*,*,*,*,regular,*")
(set_attr "length" "*,2,*,*,*,2,2,2,*,*,*,*,2,2,2,*,*")
(set_attr "fptype" "*,*,double,double,double,*,*,*,*,*,*,*,*,*,*,*,*")
(set_attr "cpu_feature" "v9,*,vis,vis,v9,fpunotv9,vis3,vis3,fpu,fpu,*,*,fpu,fpu,*,*,*")
@@ -2388,6 +2484,7 @@
stx\t%r1, %0
#"
[(set_attr "type" "visl,visl,fpmove,vismv,vismv,load,store,*,load,store,*")
+ (set_attr "subtype" "double,double,*,movdtox,movxtod,regular,*,*,regular,*,*")
(set_attr "length" "*,*,*,*,*,*,*,*,*,*,2")
(set_attr "fptype" "double,double,double,double,double,*,*,*,*,*,*")
(set_attr "cpu_feature" "vis,vis,fpu,vis3,vis3,fpu,fpu,*,*,*,*")
@@ -2917,6 +3014,7 @@
""
"lduh\t%1, %0"
[(set_attr "type" "load")
+ (set_attr "subtype" "regular")
(set_attr "us3load_type" "3cycle")])
(define_expand "zero_extendqihi2"
@@ -2933,6 +3031,7 @@
and\t%1, 0xff, %0
ldub\t%1, %0"
[(set_attr "type" "*,load")
+ (set_attr "subtype" "*,regular")
(set_attr "us3load_type" "*,3cycle")])
(define_expand "zero_extendqisi2"
@@ -2949,6 +3048,7 @@
and\t%1, 0xff, %0
ldub\t%1, %0"
[(set_attr "type" "*,load")
+ (set_attr "subtype" "*,regular")
(set_attr "us3load_type" "*,3cycle")])
(define_expand "zero_extendqidi2"
@@ -2965,6 +3065,7 @@
and\t%1, 0xff, %0
ldub\t%1, %0"
[(set_attr "type" "*,load")
+ (set_attr "subtype" "*,regular")
(set_attr "us3load_type" "*,3cycle")])
(define_expand "zero_extendhidi2"
@@ -2996,6 +3097,7 @@
"TARGET_ARCH64"
"lduh\t%1, %0"
[(set_attr "type" "load")
+ (set_attr "subtype" "regular")
(set_attr "us3load_type" "3cycle")])
;; ??? Write truncdisi pattern using sra?
@@ -3016,6 +3118,7 @@
lduw\t%1, %0
movstouw\t%1, %0"
[(set_attr "type" "shift,load,vismv")
+ (set_attr "subtype" "*,regular,movstouw")
(set_attr "cpu_feature" "*,*,vis3")
(set_attr "v3pipe" "*,*,true")])
@@ -7357,7 +7460,8 @@
[(unspec_volatile [(match_operand:SI 0 "memory_operand" "m")] UNSPECV_LDFSR)]
"TARGET_FPU"
"ld\t%0, %%fsr"
- [(set_attr "type" "load")])
+ [(set_attr "type" "load")
+ (set_attr "subtype" "regular")])
(define_insn "stfsr"
[(set (match_operand:SI 0 "memory_operand" "=m")
@@ -7721,7 +7825,8 @@
gcc_assert (locality >= 0 && locality < 4);
return prefetch_instr [read_or_write][locality == 0 ? 0 : 1];
}
- [(set_attr "type" "load")])
+ [(set_attr "type" "load")
+ (set_attr "subtype" "prefetch")])
(define_insn "prefetch_32"
[(prefetch (match_operand:SI 0 "address_operand" "p")
@@ -7746,7 +7851,8 @@
gcc_assert (locality >= 0 && locality < 4);
return prefetch_instr [read_or_write][locality == 0 ? 0 : 1];
}
- [(set_attr "type" "load")])
+ [(set_attr "type" "load")
+ (set_attr "subtype" "prefetch")])
;; Trap instructions.
@@ -7967,7 +8073,8 @@
UNSPEC_TLSIE))]
"TARGET_TLS && TARGET_ARCH32"
"ld\\t[%1 + %2], %0, %%tie_ld(%a3)"
- [(set_attr "type" "load")])
+ [(set_attr "type" "load")
+ (set_attr "subtype" "regular")])
(define_insn "tie_ld64"
[(set (match_operand:DI 0 "register_operand" "=r")
@@ -7977,7 +8084,8 @@
UNSPEC_TLSIE))]
"TARGET_TLS && TARGET_ARCH64"
"ldx\\t[%1 + %2], %0, %%tie_ldx(%a3)"
- [(set_attr "type" "load")])
+ [(set_attr "type" "load")
+ (set_attr "subtype" "regular")])
(define_insn "tie_add32"
[(set (match_operand:SI 0 "register_operand" "=r")
@@ -8037,6 +8145,7 @@
"TARGET_TLS && TARGET_ARCH32"
"ldub\t[%1 + %2], %0, %%tldo_add(%3)"
[(set_attr "type" "load")
+ (set_attr "subtype" "regular")
(set_attr "us3load_type" "3cycle")])
(define_insn "*tldo_ldub1_sp32"
@@ -8049,6 +8158,7 @@
"TARGET_TLS && TARGET_ARCH32"
"ldub\t[%1 + %2], %0, %%tldo_add(%3)"
[(set_attr "type" "load")
+ (set_attr "subtype" "regular")
(set_attr "us3load_type" "3cycle")])
(define_insn "*tldo_ldub2_sp32"
@@ -8061,6 +8171,7 @@
"TARGET_TLS && TARGET_ARCH32"
"ldub\t[%1 + %2], %0, %%tldo_add(%3)"
[(set_attr "type" "load")
+ (set_attr "subtype" "regular")
(set_attr "us3load_type" "3cycle")])
(define_insn "*tldo_ldsb1_sp32"
@@ -8096,6 +8207,7 @@
"TARGET_TLS && TARGET_ARCH64"
"ldub\t[%1 + %2], %0, %%tldo_add(%3)"
[(set_attr "type" "load")
+ (set_attr "subtype" "regular")
(set_attr "us3load_type" "3cycle")])
(define_insn "*tldo_ldub1_sp64"
@@ -8108,6 +8220,7 @@
"TARGET_TLS && TARGET_ARCH64"
"ldub\t[%1 + %2], %0, %%tldo_add(%3)"
[(set_attr "type" "load")
+ (set_attr "subtype" "regular")
(set_attr "us3load_type" "3cycle")])
(define_insn "*tldo_ldub2_sp64"
@@ -8120,6 +8233,7 @@
"TARGET_TLS && TARGET_ARCH64"
"ldub\t[%1 + %2], %0, %%tldo_add(%3)"
[(set_attr "type" "load")
+ (set_attr "subtype" "regular")
(set_attr "us3load_type" "3cycle")])
(define_insn "*tldo_ldub3_sp64"
@@ -8132,6 +8246,7 @@
"TARGET_TLS && TARGET_ARCH64"
"ldub\t[%1 + %2], %0, %%tldo_add(%3)"
[(set_attr "type" "load")
+ (set_attr "subtype" "regular")
(set_attr "us3load_type" "3cycle")])
(define_insn "*tldo_ldsb1_sp64"
@@ -8179,6 +8294,7 @@
"TARGET_TLS && TARGET_ARCH32"
"lduh\t[%1 + %2], %0, %%tldo_add(%3)"
[(set_attr "type" "load")
+ (set_attr "subtype" "regular")
(set_attr "us3load_type" "3cycle")])
(define_insn "*tldo_lduh1_sp32"
@@ -8191,6 +8307,7 @@
"TARGET_TLS && TARGET_ARCH32"
"lduh\t[%1 + %2], %0, %%tldo_add(%3)"
[(set_attr "type" "load")
+ (set_attr "subtype" "regular")
(set_attr "us3load_type" "3cycle")])
(define_insn "*tldo_ldsh1_sp32"
@@ -8214,6 +8331,7 @@
"TARGET_TLS && TARGET_ARCH64"
"lduh\t[%1 + %2], %0, %%tldo_add(%3)"
[(set_attr "type" "load")
+ (set_attr "subtype" "regular")
(set_attr "us3load_type" "3cycle")])
(define_insn "*tldo_lduh1_sp64"
@@ -8226,6 +8344,7 @@
"TARGET_TLS && TARGET_ARCH64"
"lduh\t[%1 + %2], %0, %%tldo_add(%3)"
[(set_attr "type" "load")
+ (set_attr "subtype" "regular")
(set_attr "us3load_type" "3cycle")])
(define_insn "*tldo_lduh2_sp64"
@@ -8238,6 +8357,7 @@
"TARGET_TLS && TARGET_ARCH64"
"lduh\t[%1 + %2], %0, %%tldo_add(%3)"
[(set_attr "type" "load")
+ (set_attr "subtype" "regular")
(set_attr "us3load_type" "3cycle")])
(define_insn "*tldo_ldsh1_sp64"
@@ -8272,7 +8392,8 @@
(match_operand:SI 1 "register_operand" "r"))))]
"TARGET_TLS && TARGET_ARCH32"
"ld\t[%1 + %2], %0, %%tldo_add(%3)"
- [(set_attr "type" "load")])
+ [(set_attr "type" "load")
+ (set_attr "subtype" "regular")])
(define_insn "*tldo_lduw_sp64"
[(set (match_operand:SI 0 "register_operand" "=r")
@@ -8282,7 +8403,8 @@
(match_operand:DI 1 "register_operand" "r"))))]
"TARGET_TLS && TARGET_ARCH64"
"lduw\t[%1 + %2], %0, %%tldo_add(%3)"
- [(set_attr "type" "load")])
+ [(set_attr "type" "load")
+ (set_attr "subtype" "regular")])
(define_insn "*tldo_lduw1_sp64"
[(set (match_operand:DI 0 "register_operand" "=r")
@@ -8293,7 +8415,8 @@
(match_operand:DI 1 "register_operand" "r")))))]
"TARGET_TLS && TARGET_ARCH64"
"lduw\t[%1 + %2], %0, %%tldo_add(%3)"
- [(set_attr "type" "load")])
+ [(set_attr "type" "load")
+ (set_attr "subtype" "regular")])
(define_insn "*tldo_ldsw1_sp64"
[(set (match_operand:DI 0 "register_operand" "=r")
@@ -8315,7 +8438,8 @@
(match_operand:DI 1 "register_operand" "r"))))]
"TARGET_TLS && TARGET_ARCH64"
"ldx\t[%1 + %2], %0, %%tldo_add(%3)"
- [(set_attr "type" "load")])
+ [(set_attr "type" "load")
+ (set_attr "subtype" "regular")])
(define_insn "*tldo_stb_sp32"
[(set (mem:QI (plus:SI (unspec:SI [(match_operand:SI 2 "register_operand" "r")
@@ -8520,6 +8644,7 @@
movstouw\t%1, %0
movwtos\t%1, %0"
[(set_attr "type" "visl,visl,vismv,fpload,fpstore,store,load,store,*,vismv,vismv")
+ (set_attr "subtype" "single,single,single,*,*,*,regular,*,*,movstouw,single")
(set_attr "cpu_feature" "vis,vis,vis,*,*,*,*,*,*,vis3,vis3")
(set_attr "v3pipe" "true,true,true,*,*,*,*,*,*,true,true")])
@@ -8543,6 +8668,7 @@
movxtod\t%1, %0
mov\t%1, %0"
[(set_attr "type" "visl,visl,vismv,fpload,fpstore,store,load,store,vismv,vismv,*")
+ (set_attr "subtype" "double,double,double,*,*,*,regular,*,movdtox,movxtod,*")
(set_attr "cpu_feature" "vis,vis,vis,*,*,*,*,*,vis3,vis3,*")
(set_attr "v3pipe" "true,true,true,*,*,*,*,*,*,*,*")])
@@ -8573,6 +8699,7 @@
ldd\t%1, %0
std\t%1, %0"
[(set_attr "type" "store,*,visl,visl,vismv,*,*,fpload,fpstore,load,store,*,*,*,load,store")
+ (set_attr "subtype" "*,*,double,double,double,*,*,*,*,regular,*,*,*,*,regular,*")
(set_attr "length" "*,2,*,*,*,2,2,*,*,*,*,2,2,2,*,*")
(set_attr "cpu_feature" "*,*,vis,vis,vis,vis3,vis3,*,*,*,*,*,*,*,*,*")
(set_attr "v3pipe" "*,*,true,true,true,*,*,*,*,*,*,*,*,*,*,*")
@@ -8653,6 +8780,7 @@
"TARGET_VIS"
"fp<plusminus_insn><vbits>\t%1, %2, %0"
[(set_attr "type" "fga")
+ (set_attr "subtype" "other")
(set_attr "fptype" "<vfptype>")
(set_attr "v3pipe" "true")])
@@ -8765,6 +8893,7 @@
"TARGET_VIS"
"fexpand\t%1, %0"
[(set_attr "type" "fga")
+ (set_attr "subtype" "fpu")
(set_attr "fptype" "double")])
(define_insn "fpmerge_vis"
@@ -8779,6 +8908,7 @@
"TARGET_VIS"
"fpmerge\t%1, %2, %0"
[(set_attr "type" "fga")
+ (set_attr "subtype" "fpu")
(set_attr "fptype" "double")])
;; Partitioned multiply instructions
@@ -8867,7 +8997,8 @@
[(set (reg:DI GSR_REG) (match_operand:DI 0 "arith_operand" "rI"))]
"TARGET_VIS && TARGET_ARCH64"
"wr\t%%g0, %0, %%gsr"
- [(set_attr "type" "gsr")])
+ [(set_attr "type" "gsr")
+ (set_attr "subtype" "reg")])
(define_insn "wrgsr_v8plus"
[(set (reg:DI GSR_REG) (match_operand:DI 0 "arith_operand" "I,r"))
@@ -8898,7 +9029,8 @@
[(set (match_operand:DI 0 "register_operand" "=r") (reg:DI GSR_REG))]
"TARGET_VIS && TARGET_ARCH64"
"rd\t%%gsr, %0"
- [(set_attr "type" "gsr")])
+ [(set_attr "type" "gsr")
+ (set_attr "subtype" "reg")])
(define_insn "rdgsr_v8plus"
[(set (match_operand:DI 0 "register_operand" "=r") (reg:DI GSR_REG))
@@ -8921,6 +9053,7 @@
"TARGET_VIS"
"faligndata\t%1, %2, %0"
[(set_attr "type" "fga")
+ (set_attr "subtype" "other")
(set_attr "fptype" "double")
(set_attr "v3pipe" "true")])
@@ -8933,6 +9066,7 @@
"TARGET_VIS"
"alignaddr\t%r1, %r2, %0"
[(set_attr "type" "gsr")
+ (set_attr "subtype" "alignaddr")
(set_attr "v3pipe" "true")])
(define_insn "alignaddrdi_vis"
@@ -8944,6 +9078,7 @@
"TARGET_VIS"
"alignaddr\t%r1, %r2, %0"
[(set_attr "type" "gsr")
+ (set_attr "subtype" "alignaddr")
(set_attr "v3pipe" "true")])
(define_insn "alignaddrlsi_vis"
@@ -8956,6 +9091,7 @@
"TARGET_VIS"
"alignaddrl\t%r1, %r2, %0"
[(set_attr "type" "gsr")
+ (set_attr "subtype" "alignaddr")
(set_attr "v3pipe" "true")])
(define_insn "alignaddrldi_vis"
@@ -8968,6 +9104,7 @@
"TARGET_VIS"
"alignaddrl\t%r1, %r2, %0"
[(set_attr "type" "gsr")
+ (set_attr "subtype" "alignaddr")
(set_attr "v3pipe" "true")])
(define_insn "pdist_vis"
@@ -9156,6 +9293,7 @@
"TARGET_VIS2"
"bshuffle\t%1, %2, %0"
[(set_attr "type" "fga")
+ (set_attr "subtype" "other")
(set_attr "fptype" "double")
(set_attr "v3pipe" "true")])
@@ -9260,6 +9398,7 @@
"TARGET_VIS3"
"cmask8\t%r0"
[(set_attr "type" "fga")
+ (set_attr "subtype" "cmask")
(set_attr "v3pipe" "true")])
(define_insn "cmask16<P:mode>_vis"
@@ -9270,6 +9409,7 @@
"TARGET_VIS3"
"cmask16\t%r0"
[(set_attr "type" "fga")
+ (set_attr "subtype" "cmask")
(set_attr "v3pipe" "true")])
(define_insn "cmask32<P:mode>_vis"
@@ -9280,6 +9420,7 @@
"TARGET_VIS3"
"cmask32\t%r0"
[(set_attr "type" "fga")
+ (set_attr "subtype" "cmask")
(set_attr "v3pipe" "true")])
(define_insn "fchksm16_vis"
@@ -9289,7 +9430,8 @@
UNSPEC_FCHKSM16))]
"TARGET_VIS3"
"fchksm16\t%1, %2, %0"
- [(set_attr "type" "fga")])
+ [(set_attr "type" "fga")
+ (set_attr "subtype" "fpu")])
(define_code_iterator vis3_shift [ashift ss_ashift lshiftrt ashiftrt])
(define_code_attr vis3_shift_insn
@@ -9303,7 +9445,8 @@
(match_operand:GCM 2 "register_operand" "<vconstr>")))]
"TARGET_VIS3"
"<vis3_shift_insn><vbits>\t%1, %2, %0"
- [(set_attr "type" "fga")])
+ [(set_attr "type" "fga")
+ (set_attr "subtype" "fpu")])
(define_insn "pdistn<P:mode>_vis"
[(set (match_operand:P 0 "register_operand" "=r")
@@ -9331,7 +9474,8 @@
(const_int 1))))]
"TARGET_VIS3"
"fmean16\t%1, %2, %0"
- [(set_attr "type" "fga")])
+ [(set_attr "type" "fga")
+ (set_attr "subtype" "fpu")])
(define_insn "fp<plusminus_insn>64_vis"
[(set (match_operand:V1DI 0 "register_operand" "=e")
@@ -9339,7 +9483,8 @@
(match_operand:V1DI 2 "register_operand" "e")))]
"TARGET_VIS3"
"fp<plusminus_insn>64\t%1, %2, %0"
- [(set_attr "type" "fga")])
+ [(set_attr "type" "fga")
+ (set_attr "subtype" "addsub64")])
(define_insn "<plusminus_insn>v8qi3"
[(set (match_operand:V8QI 0 "register_operand" "=e")
@@ -9347,7 +9492,8 @@
(match_operand:V8QI 2 "register_operand" "e")))]
"TARGET_VIS4"
"fp<plusminus_insn>8\t%1, %2, %0"
- [(set_attr "type" "fga")])
+ [(set_attr "type" "fga")
+ (set_attr "subtype" "other")])
(define_mode_iterator VASS [V4HI V2SI V2HI V1SI])
(define_code_iterator vis3_addsub_ss [ss_plus ss_minus])
@@ -9363,6 +9509,7 @@
"TARGET_VIS3"
"<vis3_addsub_ss_insn><vbits>\t%1, %2, %0"
[(set_attr "type" "fga")
+ (set_attr "subtype" "other")
(set_attr "v3pipe" "true")])
(define_mode_iterator VMMAX [V8QI V4HI V2SI])
@@ -9378,7 +9525,8 @@
(match_operand:VMMAX 2 "register_operand" "<vconstr>")))]
"TARGET_VIS4"
"<vis4_minmax_insn><vbits>\t%1, %2, %0"
- [(set_attr "type" "fga")])
+ [(set_attr "type" "fga")
+ (set_attr "subtype" "maxmin")])
(define_code_iterator vis4_uminmax [umin umax])
(define_code_attr vis4_uminmax_insn
@@ -9392,7 +9540,8 @@
(match_operand:VMMAX 2 "register_operand" "<vconstr>")))]
"TARGET_VIS4"
"<vis4_uminmax_insn><vbits>\t%1, %2, %0"
- [(set_attr "type" "fga")])
+ [(set_attr "type" "fga")
+ (set_attr "subtype" "maxmin")])
;; The use of vis3_addsub_ss_patname in the VIS4 instruction below is
;; intended.
@@ -9402,7 +9551,8 @@
(match_operand:V8QI 2 "register_operand" "e")))]
"TARGET_VIS4"
"<vis3_addsub_ss_insn>8\t%1, %2, %0"
- [(set_attr "type" "fga")])
+ [(set_attr "type" "fga")
+ (set_attr "subtype" "other")])
(define_mode_iterator VAUS [V4HI V8QI])
(define_code_iterator vis4_addsub_us [us_plus us_minus])
@@ -9417,7 +9567,8 @@
(match_operand:VAUS 2 "register_operand" "<vconstr>")))]
"TARGET_VIS4"
"<vis4_addsub_us_insn><vbits>\t%1, %2, %0"
- [(set_attr "type" "fga")])
+ [(set_attr "type" "fga")
+ (set_attr "subtype" "other")])
(define_insn "fucmp<gcond:code>8<P:mode>_vis"
[(set (match_operand:P 0 "register_operand" "=r")
--
2.3.4