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[patch][arm] Clean up generation of BE8 format images.
- From: "Richard Earnshaw (lists)" <Richard dot Earnshaw at arm dot com>
- To: gcc-patches <gcc-patches at gcc dot gnu dot org>
- Date: Mon, 3 Jul 2017 14:23:23 +0100
- Subject: [patch][arm] Clean up generation of BE8 format images.
- Authentication-results: sourceware.org; auth=none
The existing code in arm/bpabi.h was quite fragile and relied on matching
specific CPU and/or architecture names. The introduction of the option
format for -mcpu and -march broke that in a way that would be non-trivial
to fix by updating the list. The hook in that file was always a pain
as it required every new CPU being added to be add an update here as well
(easy to miss).
I've fixed that problem once and for all by adding a new callback into
the driver to select the correct BE8 behaviour. This uses features in
the ISA capabilities list to select whether or not to use BE8 format
during linking.
I also noticed that if the user happened to pass both -mbig-endian and
-mlittle-endian on the command line then the linker spec rules would
get somewhat confused and potentially do the wrong thing. I've fixed that
by marking these options as opposites in the option descriptions. The
driver will now automatically suppress overridden options leading to the
correct desired behavior.
Whilst fixing this I noticed a couple of anomolus cases in the
existing BE8 support: we were not generating BE8 format for ARMv6 or
ARMv7-R targets. While the ARMv6 status was probably deliberate at
the time, this is probably not a good idea in the long term as the
alternative, BE32, has been deprecated by ARM. After discussion with
a couple of colleagues I've decided to change this, but to then add an
option to restore the existing behaviour at the user's option. So
this patch introduces two new options (opposites) -mbe8 and -mbe32.
This is a quiet behavior change, so I'll add a comment to the release
notes shortly.
* common/config/arm/arm-common.c (arm_be8_option): New function.
* config/arm/arm-isa.h (isa_feature): Add new feature bit isa_bit_be8.
(ISA_ARMv6): Add isa_bit_be8.
* config/arm/arm.h (arm_be8_option): Add prototype.
(BE8_SPEC_FUNCTION): New define.
(EXTRA_SPEC_FUNCTIONS): Add BE8_SPEC_FUNCTION.
* config/arm/arm.opt (mbig-endian): Mark as Negative of mlittle-endian.
(mlittle-endian): Similarly.
(mbe8, mbe32): New options.
* config/arm/bpabi.h (BE8_LINK_SPEC): Call arm_be8_option.
* doc/invoke.texi (ARM Options): Document -mbe8 and -mbe32.
diff --git a/gcc/common/config/arm/arm-common.c b/gcc/common/config/arm/arm-common.c
index d06c39b..b6244d6 100644
--- a/gcc/common/config/arm/arm-common.c
+++ b/gcc/common/config/arm/arm-common.c
@@ -761,6 +761,63 @@ arm_canon_arch_option (int argc, const char **argv)
return canonical_arch;
}
+/* If building big-endian on a BE8 target generate a --be8 option for
+ the linker. Takes four types of option: "little" - little-endian;
+ "big" - big-endian; "be8" - force be8 iff big-endian; and "arch"
+ "<arch-name>" (two arguments) - the target architecture. The
+ parameter names are generated by the driver from the command-line
+ options. */
+const char *
+arm_be8_option (int argc, const char **argv)
+{
+ int endian = TARGET_ENDIAN_DEFAULT;
+ const char *arch = NULL;
+ int arg;
+ bool force = false;
+
+ for (arg = 0; arg < argc; arg++)
+ {
+ if (strcmp (argv[arg], "little") == 0)
+ endian = 0;
+ else if (strcmp (argv[arg], "big") == 0)
+ endian = 1;
+ else if (strcmp (argv[arg], "be8") == 0)
+ force = true;
+ else if (strcmp (argv[arg], "arch") == 0)
+ {
+ arg++;
+ gcc_assert (arg < argc);
+ arch = argv[arg];
+ }
+ else
+ gcc_unreachable ();
+ }
+
+ /* Little endian - no be8 option. */
+ if (!endian)
+ return "";
+
+ if (force)
+ return "--be8";
+
+ /* Arch might not be set iff arm_canon_arch (above) detected an
+ error. Do nothing in that case. */
+ if (!arch)
+ return "";
+
+ const arch_option *selected_arch
+ = arm_parse_arch_option_name (all_architectures, "-march", arch);
+
+ /* Similarly if the given arch option was itself invalid. */
+ if (!selected_arch)
+ return "";
+
+ if (check_isa_bits_for (selected_arch->common.isa_bits, isa_bit_be8))
+ return "--be8";
+
+ return "";
+}
+
#undef ARM_CPU_NAME_LENGTH
diff --git a/gcc/config/arm/arm-isa.h b/gcc/config/arm/arm-isa.h
index 4b5a0f6..c0c2cce 100644
--- a/gcc/config/arm/arm-isa.h
+++ b/gcc/config/arm/arm-isa.h
@@ -40,7 +40,8 @@ enum isa_feature
isa_bit_ARMv6, /* Architecture rel 6. */
isa_bit_ARMv6k, /* Architecture rel 6k. */
isa_bit_thumb2, /* Thumb-2. */
- isa_bit_notm, /* Instructions that are not present in 'M' profile. */
+ isa_bit_notm, /* Instructions not present in 'M' profile. */
+ isa_bit_be8, /* Architecture uses be8 mode in big-endian. */
isa_bit_tdiv, /* Thumb division instructions. */
isa_bit_ARMv7em, /* Architecture rel 7e-m. */
isa_bit_ARMv7, /* Architecture rel 7. */
@@ -101,7 +102,7 @@ enum isa_feature
#define ISA_ARMv5e ISA_ARMv5, isa_bit_ARMv5e
#define ISA_ARMv5te ISA_ARMv5e, isa_bit_thumb
#define ISA_ARMv5tej ISA_ARMv5te
-#define ISA_ARMv6 ISA_ARMv5te, isa_bit_ARMv6
+#define ISA_ARMv6 ISA_ARMv5te, isa_bit_ARMv6, isa_bit_be8
#define ISA_ARMv6j ISA_ARMv6
#define ISA_ARMv6k ISA_ARMv6, isa_bit_ARMv6k
#define ISA_ARMv6z ISA_ARMv6
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index 6bc36bba..c803d44 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -2257,11 +2257,16 @@ const char *arm_canon_arch_option (int argc, const char **argv);
#define CANON_ARCH_SPEC_FUNCTION \
{ "canon_arch", arm_canon_arch_option },
+const char *arm_be8_option (int argc, const char **argv);
+#define BE8_SPEC_FUNCTION \
+ { "be8_linkopt", arm_be8_option },
+
# define EXTRA_SPEC_FUNCTIONS \
MCPU_MTUNE_NATIVE_FUNCTIONS \
ASM_CPU_SPEC_FUNCTIONS \
CANON_ARCH_SPEC_FUNCTION \
- TARGET_MODE_SPEC_FUNCTIONS
+ TARGET_MODE_SPEC_FUNCTIONS \
+ BE8_SPEC_FUNCTION
/* Automatically add -mthumb for Thumb-only targets if mode isn't specified
via the configuration option --with-mode or via the command line. The
diff --git a/gcc/config/arm/arm.opt b/gcc/config/arm/arm.opt
index dad5257..b6c707b 100644
--- a/gcc/config/arm/arm.opt
+++ b/gcc/config/arm/arm.opt
@@ -95,7 +95,7 @@ Target Report RejectNegative Negative(mthumb) InverseMask(THUMB)
Generate code in 32 bit ARM state.
mbig-endian
-Target Report RejectNegative Mask(BIG_END)
+Target Report RejectNegative Negative(mlittle-endian) Mask(BIG_END)
Assume target CPU is configured as big endian.
mcallee-super-interworking
@@ -160,7 +160,7 @@ mhard-float
Target RejectNegative Alias(mfloat-abi=, hard) Undocumented
mlittle-endian
-Target Report RejectNegative InverseMask(BIG_END)
+Target Report RejectNegative Negative(mbig-endian) InverseMask(BIG_END)
Assume target CPU is configured as little endian.
mlong-calls
@@ -286,3 +286,11 @@ Assume unified syntax for inline assembly code.
mpure-code
Target Report Var(target_pure_code) Init(0)
Do not allow constant data to be placed in code sections.
+
+mbe8
+Target Report RejectNegative Negative(mbe32) Mask(BE8)
+When linking for big-endian targets, generate a BE8 format image.
+
+mbe32
+Target Report RejectNegative Negative(mbe8) InverseMask(BE8)
+When linking for big-endian targets, generate a legacy BE32 format image.
diff --git a/gcc/config/arm/bpabi.h b/gcc/config/arm/bpabi.h
index d38863a..2f41c4f 100644
--- a/gcc/config/arm/bpabi.h
+++ b/gcc/config/arm/bpabi.h
@@ -26,7 +26,7 @@
/* Use the AAPCS ABI by default. */
#define ARM_DEFAULT_ABI ARM_ABI_AAPCS
-/* Assume that AAPCS ABIs should adhere to the full BPABI. */
+/* Assume that AAPCS ABIs should adhere to the full BPABI. */
#define TARGET_BPABI (TARGET_AAPCS_BASED)
/* BPABI targets use EABI frame unwinding tables. */
@@ -55,84 +55,11 @@
#define TARGET_FIX_V4BX_SPEC " %{mcpu=arm8|mcpu=arm810|mcpu=strongarm*"\
"|march=armv4|mcpu=fa526|mcpu=fa626:--fix-v4bx}"
-#if TARGET_BIG_ENDIAN_DEFAULT
-#define BE8_LINK_SPEC \
- " %{!mlittle-endian:%{march=armv7-a|mcpu=cortex-a5 \
- |mcpu=cortex-a7 \
- |mcpu=cortex-a8|mcpu=cortex-a9|mcpu=cortex-a15 \
- |mcpu=cortex-a12|mcpu=cortex-a17 \
- |mcpu=cortex-a15.cortex-a7 \
- |mcpu=cortex-a17.cortex-a7 \
- |mcpu=marvell-pj4 \
- |mcpu=cortex-a32 \
- |mcpu=cortex-a35 \
- |mcpu=cortex-a53 \
- |mcpu=cortex-a57 \
- |mcpu=cortex-a57.cortex-a53 \
- |mcpu=cortex-a72 \
- |mcpu=cortex-a72.cortex-a53 \
- |mcpu=cortex-a73 \
- |mcpu=cortex-a73.cortex-a35 \
- |mcpu=cortex-a73.cortex-a53 \
- |mcpu=exynos-m1 \
- |mcpu=xgene1 \
- |mcpu=cortex-m1.small-multiply \
- |mcpu=cortex-m0.small-multiply \
- |mcpu=cortex-m0plus.small-multiply \
- |mcpu=generic-armv7-a \
- |march=armv7ve \
- |march=armv7-m|mcpu=cortex-m3 \
- |march=armv7e-m|mcpu=cortex-m4|mcpu=cortex-m7 \
- |march=armv6-m|mcpu=cortex-m0 \
- |march=armv8-a \
- |march=armv8-a+crc \
- |march=armv8.1-a \
- |march=armv8.1-a+crc \
- |march=armv8.2-a \
- |march=armv8.2-a+fp16 \
- |march=armv8-m.base|mcpu=cortex-m23 \
- |march=armv8-m.main \
- |march=armv8-m.main+dsp|mcpu=cortex-m33 \
- :%{!r:--be8}}}"
-#else
-#define BE8_LINK_SPEC \
- " %{mbig-endian:%{march=armv7-a|mcpu=cortex-a5 \
- |mcpu=cortex-a7 \
- |mcpu=cortex-a8|mcpu=cortex-a9|mcpu=cortex-a15 \
- |mcpu=cortex-a12|mcpu=cortex-a17 \
- |mcpu=cortex-a15.cortex-a7 \
- |mcpu=cortex-a17.cortex-a7 \
- |mcpu=cortex-a35 \
- |mcpu=cortex-a53 \
- |mcpu=cortex-a57 \
- |mcpu=cortex-a57.cortex-a53 \
- |mcpu=cortex-a72 \
- |mcpu=cortex-a72.cortex-a53 \
- |mcpu=cortex-a73 \
- |mcpu=cortex-a73.cortex-a35 \
- |mcpu=cortex-a73.cortex-a53 \
- |mcpu=exynos-m1 \
- |mcpu=xgene1 \
- |mcpu=cortex-m1.small-multiply \
- |mcpu=cortex-m0.small-multiply \
- |mcpu=cortex-m0plus.small-multiply \
- |mcpu=marvell-pj4 \
- |mcpu=generic-armv7-a \
- |march=armv7ve \
- |march=armv7-m|mcpu=cortex-m3 \
- |march=armv7e-m|mcpu=cortex-m4|mcpu=cortex-m7 \
- |march=armv6-m|mcpu=cortex-m0 \
- |march=armv8-a \
- |march=armv8-a+crc \
- |march=armv8.1-a \
- |march=armv8.1-a+crc \
- |march=armv8.2-a \
- |march=armv8.2-a+fp16 \
- |march=armv8-m.base|mcpu=cortex-m23 \
- |march=armv8-m.main \
- |march=armv8-m.main+dsp|mcpu=cortex-m33 \
- :%{!r:--be8}}}"
-#endif
+#define BE8_LINK_SPEC \
+ "%{!r:%{!mbe32:%:be8_linkopt(%{mlittle-endian:little}" \
+ " %{mbig-endian:big}" \
+ " %{mbe8:be8}" \
+ " %{march=*:arch %*})}}"
/* Tell the assembler to build BPABI binaries. */
#undef SUBTARGET_EXTRA_ASM_SPEC
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index d1e097b..bef92a82 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -15188,6 +15188,15 @@ the default for all standard configurations.
Generate code for a processor running in big-endian mode; the default is
to compile code for a little-endian processor.
+@item -mbe8
+@itemx -mbe32
+@opindex mbe8
+When linking a big-endian image select between BE8 and BE32 formats.
+The option has no effect for little-endian images and is ignored. The
+default is dependent on the selected target architecture. For ARMv6
+and later architectures the default is BE8, for older architectures
+the default is BE32. BE32 format has been deprecated by ARM.
+
@item -march=@var{name@r{[}+extension@dots{}@r{]}}
@opindex march
This specifies the name of the target ARM architecture. GCC uses this