This is the mail archive of the
gcc-patches@gcc.gnu.org
mailing list for the GCC project.
Re: [PATCH][AArch64] Allow const0_rtx operand for atomic compare-exchange patterns
- From: James Greenhalgh <james dot greenhalgh at arm dot com>
- To: Kyrill Tkachov <kyrylo dot tkachov at foss dot arm dot com>
- Cc: GCC Patches <gcc-patches at gcc dot gnu dot org>, Marcus Shawcroft <marcus dot shawcroft at arm dot com>, Richard Earnshaw <Richard dot Earnshaw at arm dot com>, <nd at arm dot com>
- Date: Tue, 6 Jun 2017 14:16:22 +0100
- Subject: Re: [PATCH][AArch64] Allow const0_rtx operand for atomic compare-exchange patterns
- Authentication-results: sourceware.org; auth=none
- Authentication-results: spf=pass (sender IP is 217.140.96.140) smtp.mailfrom=arm.com; gcc.gnu.org; dkim=none (message not signed) header.d=none;gcc.gnu.org; dmarc=bestguesspass action=none header.from=arm.com;
- Nodisclaimer: True
- References: <58B56D3E.3090704@foss.arm.com>
- Spamdiagnosticmetadata: NSPM
- Spamdiagnosticoutput: 1:99
On Tue, Feb 28, 2017 at 12:29:50PM +0000, Kyrill Tkachov wrote:
> Hi all,
>
> For the testcase in this patch we currently generate:
> foo:
> mov w1, 0
> ldaxr w2, [x0]
> cmp w2, 3
> bne .L2
> stxr w3, w1, [x0]
> cmp w3, 0
> .L2:
> cset w0, eq
> ret
>
> Note that the STXR could have been storing the WZR register instead of moving zero into w1.
> This is due to overly strict predicates and constraints in the store exclusive pattern and the
> atomic compare exchange expanders and splitters.
> This simple patch fixes that in the patterns concerned and with it we can generate:
> foo:
> ldaxr w1, [x0]
> cmp w1, 3
> bne .L2
> stxr w2, wzr, [x0]
> cmp w2, 0
> .L2:
> cset w0, eq
> ret
>
>
> Bootstrapped and tested on aarch64-none-linux-gnu.
> Ok for GCC 8?
OK.
Thanks,
James
> 2017-02-28 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
>
> * config/aarch64/atomics.md (atomic_compare_and_swap<mode> expander):
> Use aarch64_reg_or_zero predicate for operand 4.
> (aarch64_compare_and_swap<mode> define_insn_and_split):
> Use aarch64_reg_or_zero predicate for operand 3. Add 'Z' constraint.
> (aarch64_store_exclusive<mode>): Likewise for operand 2.
>
> 2017-02-28 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
>
> * gcc.target/aarch64/atomic_cmp_exchange_zero_reg_1.c: New test.