[PATCH], PR target/80510, Optimize offsettable memory references on power7/power8

[Michael Meissner <meissner at linux dot vnet dot ibm dot com>]

When I was fixing PR target/68163, I noticed there was a wider problem, and
opened up PR 80510.

The problem is if the DImode, DFmode, and SFmode are allowed in Altivec
registers before ISA 3.0, and the compiler wants to do an offsettable store.
The compiler generates a move from an Altivec register to a traditional
floating point register, and then the compiler generates the STFD or STFS
instruction.

This code adds peephole2's that notices there is a move from an altivec
regsiter to fpr register and store, it changes this load the offset into a GPR,
and do the indexed store from the Altivec register.  I also added code to do
the reverse (notice if there is a load to a FPR register and copy it to an
Altivec register) and use an indexed load.

I ran the Spec 2006 floating point suite with this patch, and the LBM benchmark
shows a nearly 3% gain with this patch, and there were no significant
regressions.  I also bootstrapped the compiler and insured there were no
regressions.  Can I check this into GCC 8?  How about GCC 7?

Note, using peepholes are a quick way to fix the particular problem.  However,
it would be nice long term to arrange things so the back end can tell the
register allocator to load up the offset into a register, instead of doing the
move/store.  I tried various modifications to secondary reload, but I wasn't
able to get it to change behavor.

[gcc]
2017-05-12  Michael Meissner  <meissner@linux.vnet.ibm.com>

	PR target/80510
	* config/rs6000/predicates.md (simple_offsettable_mem_operand):
	New predicate.

	* config/rs6000/rs6000.md (ALTIVEC_DFORM): New iterator.
	(define_peephole2 for Altivec d-form load): Add peepholes to catch
	cases where the register allocator uses a move and an offsettable
	memory operation to/from a FPR register on ISA 2.06/2.07.
	(define_peephole2 for Altivec d-form store): Likewise.

[gcc/testsuite]
2017-05-12  Michael Meissner  <meissner@linux.vnet.ibm.com>

	PR target/80510
	* gcc.target/powerpc/pr80510-1.c: New test.
	* gcc.target/powerpc/pr80510-2.c: Likewise.



-- 
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.vnet.ibm.com, phone: +1 (978) 899-4797

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