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This patch reworks the original patch I attached to the bug report, to try and make it less hacky. It separates the bswap insns where there is hardware support into separate read, write, and register swap instructions. This is because the register allocators will try to push the bswap value in a register to the stack and do the load based swap with reverse bytes. Reload fumbles in certain conditions. LRA generates working code, but the store and the load with byte reverse from the same location, can slow things down compared to the operation on registers. I only did this optimization where we had the hardware support (i.e. bswap for HImode all of the time, bswap for SImode all of the time, and bswap for DImode if we are executing 64-bit instructions and the machine has LDBRX/STDBRX -- power7 and newer/cell ppc). I have done bootstrap builds on a little endian power8 system, on a big endian power8 system, and a big endian power7 system (both 32/64-bit support on this last system). There were no regressions. I applied the patches to GCC 6, and the compiler builds and has no regressions on a little endian power8 system. I built spec 2006 benchmarks with the GCC 7 compiler. There are 12 benchmarks that generate one or more load/store with byte swap instructions (perlbench, gcc, gamess, milc, zeusmp, calculix, h264ref, tonto, omnetpp, wrf, sphinx3, xalancbmk). I compared the instructions generated. 10 of the benchmarks generated the same instructions. Milc generated 1 less load with byte swap instruction and 1 more store with byte swap instruction. Sphinx3 generated 6 less load with byte swap instructions and 6 more store with byte swap instructions. So I count this as the same level of byte swapping is being generated. Can I apply the patch to the GCC 7 trunk? Since the patch shows up as an abort in GCC 6 and not in GCC 7 (unless you disable LRA), I would like to apply the patch as soon as possible to the GCC 6 branch. -- Michael Meissner, IBM IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA email: meissner@linux.vnet.ibm.com, phone: +1 (978) 899-4797
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