This is the mail archive of the
gcc-patches@gcc.gnu.org
mailing list for the GCC project.
Re: [PATCH][AArch64] Add aes and sha reservations for Thunderx2t99
- From: James Greenhalgh <james dot greenhalgh at arm dot com>
- To: "Hurugalawadi, Naveen" <Naveen dot Hurugalawadi at cavium dot com>
- Cc: "gcc-patches at gcc dot gnu dot org" <gcc-patches at gcc dot gnu dot org>, "Pinski, Andrew" <Andrew dot Pinski at cavium dot com>, Richard Earnshaw <Richard dot Earnshaw at arm dot com>, Marcus Shawcroft <marcus dot shawcroft at arm dot com>, <nd at arm dot com>
- Date: Wed, 8 Mar 2017 17:39:39 +0000
- Subject: Re: [PATCH][AArch64] Add aes and sha reservations for Thunderx2t99
- Authentication-results: sourceware.org; auth=none
- Authentication-results: spf=pass (sender IP is 217.140.96.140) smtp.mailfrom=arm.com; cavium.com; dkim=none (message not signed) header.d=none;cavium.com; dmarc=bestguesspass action=none header.from=arm.com;
- Nodisclaimer: True
- References: <CO2PR07MB26945BE5C89873CA5C309A27832C0@CO2PR07MB2694.namprd07.prod.outlook.com>
- Spamdiagnosticmetadata: NSPM
- Spamdiagnosticoutput: 1:99
On Mon, Mar 06, 2017 at 05:09:58AM +0000, Hurugalawadi, Naveen wrote:
> Hi,
>
> Please find attached the patch that adds aes and sha reservations for
> Thunderx2t99.
>
> Bootstrapped and Regression tested on aarch64-thunder-linux.
> Please review the patch and let us know if its okay for Stage-1?
>
> Thanks,
> Naveen
>
> 2017-03-06 Julian Brown <julian@codesourcery.com>
> Naveen H.S <Naveen.Hurugalawadi@cavium.com>
>
> * config/aarch64/thunderx2t99.md (thunderx2t99_crc): New Reservation.
> diff --git a/gcc/config/aarch64/thunderx2t99.md b/gcc/config/aarch64/thunderx2t99.md
> index f807547..2eb136b 100644
> --- a/gcc/config/aarch64/thunderx2t99.md
> +++ b/gcc/config/aarch64/thunderx2t99.md
> @@ -443,7 +443,22 @@
> (eq_attr "type" "neon_store2_one_lane,neon_store2_one_lane_q"))
> "thunderx2t99_ls01,thunderx2t99_f01")
>
> +;; Crypto extensions.
> +
> +; FIXME: Forwarding path for aese/aesmc or aesd/aesimc pairs?
Do you need these if you've enabled instruction fusion?
I'm not sure on the exact mechanics of how instruction fusion works, and
whether you'd get further scheduling benefits from modeling a forwarding
path if one exists.
Regardless, this patch is OK for Stage 1.
Thanks,
James
> +(define_insn_reservation "thunderx2t99_aes" 5
> + (and (eq_attr "tune" "thunderx2t99")
> + (eq_attr "type" "crypto_aese,crypto_aesmc"))
> + "thunderx2t99_f1")
> +
> (define_insn_reservation "thunderx2t99_pmull" 5
> (and (eq_attr "tune" "thunderx2t99")
> (eq_attr "type" "crypto_pmull"))
> "thunderx2t99_f1")
> +
> +(define_insn_reservation "thunderx2t99_sha" 7
> + (and (eq_attr "tune" "thunderx2t99")
> + (eq_attr "type" "crypto_sha1_fast,crypto_sha1_xor,crypto_sha1_slow,\
> + crypto_sha256_fast,crypto_sha256_slow"))
> + "thunderx2t99_f1")