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Re: [PATCH] Add AVX512 k-mask intrinsics
- From: Uros Bizjak <ubizjak at gmail dot com>
- To: Andrew Senkevich <andrew dot n dot senkevich at gmail dot com>
- Cc: GCC Patches <gcc-patches at gcc dot gnu dot org>
- Date: Thu, 15 Dec 2016 17:51:09 +0100
- Subject: Re: [PATCH] Add AVX512 k-mask intrinsics
- Authentication-results: sourceware.org; auth=none
- References: <CAFULd4asNZGmBcB_f0p_JAYs-uPx-woFf1tP2wJu2WUA5yovtQ@mail.gmail.com> <CAMXFM3vqO5PPn1HA8sucPR1Hf-wJRg4n334HC065ePJV6ja3aA@mail.gmail.com> <CAFULd4ahdQjg1o+3Z19jzk866SBtUq00nLiVQ_3SxjLQQRq_kw@mail.gmail.com> <CAFULd4bB2+xXUOSNe6BzoQyZd5WJOWXh4vmdwmM4ZAgGrYvKDQ@mail.gmail.com> <CAMXFM3tgs1wdFn0oejd7vOHbgebUdQ_7O3DcdX99e0-JUTVESg@mail.gmail.com> <CAFULd4ZROM5_jOy3KR6Zxs_X-0ZA_Fz6d16nogvjQ7L4x4Td-A@mail.gmail.com> <CAMXFM3uJ8DiaEPDYL9WBx6=v-ObWVh=nVx_3MBQN3D_REE-6sA@mail.gmail.com> <CAFULd4Zj1Fj0HUSEC_V71Vnutmw0=OU5HSKJFeOCdAY1rWn++g@mail.gmail.com> <CAMXFM3v5V+XeG1a7YgBLUUo6BS6h6SPRqkhphk2w4o+nKtP-vA@mail.gmail.com> <CAFULd4YOmYoYV4ChYPPB0d3L5MyJOBUdfQRLb1f2hC973iLz0g@mail.gmail.com> <CAMXFM3vC-3bMgQaQ2bnjDU7oQMPdvhurzgOFftZHqzNXAw=WgA@mail.gmail.com>
On Thu, Dec 15, 2016 at 2:31 PM, Andrew Senkevich
<andrew.n.senkevich@gmail.com> wrote:
> 2016-12-14 22:55 GMT+03:00 Uros Bizjak <ubizjak@gmail.com>:
>> On Wed, Dec 14, 2016 at 8:04 PM, Andrew Senkevich
>> <andrew.n.senkevich@gmail.com> wrote:
>>
>>> here is the second part of k-mask intrinsics, is it Ok?
>>
>>> --- a/gcc/config/i386/sse.md
>>> +++ b/gcc/config/i386/sse.md
>>> @@ -1309,12 +1309,30 @@
>>> ;; Mask variant shift mnemonics
>>> (define_code_attr mshift [(ashift "shiftl") (lshiftrt "shiftr")])
>>>
>>> +(define_expand "kmovb"
>>> + [(set (match_operand:QI 0 "nonimmediate_operand")
>>> + (match_operand:QI 1 "nonimmediate_operand"))]
>>> + "TARGET_AVX512DQ
>>> + && !(MEM_P (operands[0]) && MEM_P (operands[1]))")
>>> +
>>> (define_expand "kmovw"
>>> [(set (match_operand:HI 0 "nonimmediate_operand")
>>> (match_operand:HI 1 "nonimmediate_operand"))]
>>> "TARGET_AVX512F
>>> && !(MEM_P (operands[0]) && MEM_P (operands[1]))")
>>>
>>> +(define_expand "kmovd"
>>> + [(set (match_operand:SI 0 "nonimmediate_operand")
>>> + (match_operand:SI 1 "nonimmediate_operand"))]
>>> + "TARGET_AVX512BW
>>> + && !(MEM_P (operands[0]) && MEM_P (operands[1]))")
>>> +
>>> +(define_expand "kmovq"
>>> + [(set (match_operand:DI 0 "nonimmediate_operand")
>>> + (match_operand:DI 1 "nonimmediate_operand"))]
>>> + "TARGET_AVX512BW
>>> + && !(MEM_P (operands[0]) && MEM_P (operands[1]))")
>>> +
>>> (define_insn "k<code><mode>"
>>> [(set (match_operand:SWI1248_AVX512BW 0 "register_operand" "=k")
>>> (any_logic:SWI1248_AVX512BW
>>
>> All the above patterns can be macroized with the following patch:
>>
>> --cut here--
>> Index: sse.md
>> ===================================================================
>> --- sse.md (revision 243651)
>> +++ sse.md (working copy)
>> @@ -1309,9 +1309,9 @@
>> ;; Mask variant shift mnemonics
>> (define_code_attr mshift [(ashift "shiftl") (lshiftrt "shiftr")])
>>
>> -(define_expand "kmovw"
>> - [(set (match_operand:HI 0 "nonimmediate_operand")
>> - (match_operand:HI 1 "nonimmediate_operand"))]
>> +(define_expand "kmov<mskmodesuffix>"
>> + [(set (match_operand:SWI1248_AVX512BWDQ 0 "nonimmediate_operand")
>> + (match_operand:SWI1248_AVX512BWDQ 1 "nonimmediate_operand"))]
>> "TARGET_AVX512F
>> && !(MEM_P (operands[0]) && MEM_P (operands[1]))")
>>
>> --cut here--
>>
>> Please also post ChangeLog entry.
>
> Thanks,
>
> here is with ChangeLogs and renamed internal __builtin_ia32_kmov* to
> match instruction names.
> For __builtin_ia32_kmov16 change I will follow up for update in branches.
>
> Regtested on x86_64-linux-gnu, Ok for trunk?
OK.
Thanks,
Uros.