[PATCH] combine: Simplify "(and (subreg (zero_extract" in change_zero_ext.

[Dominik Vogt <vogt at linux dot vnet dot ibm dot com>]

The attached patch takes care of the problem described below.

(I tried to stick the new code into the regular combine-simplify
stuff, but that does not work well.  At the time when
combine_simplify_rtx is called, it's not known whether
change_zero_ext will expand the ZERO_EXTRACT to "(and (lshiftrt"
and does not know the constant it could pull out of the zero
extract, so this is why the patch does it in change_zero_ext().)

To take the code wrapping the ZERO_EXTRACT into account it was
necessary to move the code dealing with the set source to a
separate function that is called recursively.

The patch has been bootstrapped and regression tested on s390 and
s390x and has no noticeably bad side effects so far.

P.S.:  Is it necessary to pass PITER by pointer or could it be
passed simply by value?

On Wed, Dec 07, 2016 at 09:21:35PM +0100, Dominik Vogt wrote:
> I guess this has something to do with the extra logic for
> replacing zero_extract with "(and (lshiftrt ...".  In one specific
> situation, the replacement generates something odd.  Initially,
> there are these insns:
> 
> --
> (insn 6 3 7 2 (set (reg:DI 67)
>         (lshiftrt:DI (reg:DI 2 %r2 [ v_x ])
>             (const_int 12 [0xc])))
> 
> (insn 7 6 8 2 (parallel [
>             (set (reg:SI 66 [ v_conv ])
>                 (and:SI (subreg:SI (reg:DI 67) 4)
>                     (const_int -4 [0xfffffffffffffffc])))
>             (clobber (reg:CC 33 %cc))
> --
> 
> Combine tries:
> 
> --
> Trying 6 -> 7:
> Failed to match this instruction:
> (parallel [
>         (set (reg:SI 66 [ v_conv ])
>             (and:SI (subreg:SI (zero_extract:DI (reg:DI 2 %r2 [
> v_x ])
>                         (const_int 32 [0x20])
>                         (const_int 20 [0x14])) 4)
>                 (const_int -4 [0xfffffffffffffffc])))
>         (clobber (reg:CC 33 %cc))
>     ])
> ...
>         (const_int -4 [0xfffffffffffffffc])))
> Failed to match this instruction:
> (set (reg:SI 66 [ v_conv ])
>     (and:SI (subreg:SI (and:DI (lshiftrt:DI (reg:DI 2 %r2 [ v_x ])
>     ^^^^^^^^^^^^^^^^^^^^^^^^^^
>                     (const_int 12 [0xc]))
>                 (const_int 4294967295 [0xffffffff])) 4)
>         (const_int -4 [0xfffffffffffffffc])))
> 
> --
> 
> The two "and"s could be combined into a single one.  Now, I can of
> course add some pattern to the backend to deal with it, but this
> should probably be handled in combin?
> 
> (The C code is (with the proper types):)
> --
> #define i64 signed long long 
> #define ui64 unsigned long long 
> #define i32 signed int 
> #define ui32 unsigned int 
> i32 f43 (i64 v_x) 
> { 
>   i64 v_shr3 = ((ui64)v_x) >> 12; 
>   i32 v_shr3_tr = (ui32)v_shr3; 
>   i32 v_conv = v_shr3_tr & -4; 
>   return v_conv; 
> } 

Ciao

Dominik ^_^  ^_^

-- 

Dominik Vogt
IBM Germany

Attachment: 0001-ChangeLog
Description: Text document

Attachment: 0001-combine-Simplify-and-subreg-zero_extract-in-change_z.patch
Description: Text document