[PATCH] Add ISA 3.0 PowerPC support for VEXTU{B,H,W}{L,R}X instructions

[Michael Meissner <meissner at linux dot vnet dot ibm dot com>]

This patch adds support to use the ISA 3.0 VEXTU{B,H,W}{L,R}X byte extract
instructions in the PowerPC.  These instructions extract a byte, 16-bit
half-word, or 32-bit word from a vector register using a variable index in a
general purpose register, and put the result in a general purpose register.

Previous code added support for VEXTRACTU{B,H} and XXEXTRACTUW instructions
which took a fixed index and put the result into a vector register.  However,
for small integer types, it is often preferred to return the value in a GPR.

For most code, the effect of adding these instructions means that the compiler
will generate a LI instruction (to load up the byte offset into a GPR register)
instead of a MFVSR{W,D} instruction (to move the result into a GPR from a
vector register).

Because the code now favors doing an extract with the result going in a GPR, I
added combiner code so that if you do a vector extract and convert that value
to a hardware supported floating point type, the value is left in the vector
registers, and move to/from vector register instructions are not needed.

I have done bootstrap builds on a little endian 64-bit power8 system and a big
endian power7 system wit both 32/64-bit support.  There were no regressions.
In addition, I ran all of the run vector extract tests under the simulator, and
they all ran correctly.  I also added and ran tests to verify that vector
extract being converted to floating point now generates the correct code.

Can I install the patch into the trunk?

[gcc]
2016-12-09  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* config/rs6000/rs6000.c (rs6000_split_vec_extract_var): On ISA
	3.0/power9, add support to use the VEXTU{B,H,W}{L,R}X extract
	instructions.

	* config/rs6000/vsx.md (VSr2): Add IEEE 128-bit floating point
	type constraint registers.
	(VSr3): Likewise.
	(vsx_extract_<mode>_p9): Add support for the ISA 3.0/power9
	VEXTU{B,H,W}{L,R}X extract instructions.
	(vsx_extract_<mode>_p9 splitter): Add splitter to load up the
	extract byte position into the GPR if we are using the
	VEXTU{B,H,W}{L,R}X extract instructions.
	(vsx_extract_<mode>_di_p9): Support extracts to GPRs.
	(vsx_extract_<mode>_var): Likewise.
	(vsx_extract_<VSX_EXTRACT_I:mode>_<SDI:mode>_var): New combiner
	insn to combine vector extracts with zero_extend.
	(vsx_ext_<VSX_EXTRACT_I:VS_scalar>_fl_<FL_CONV:mode>): Optimize
	extracting a small integer vector element and converting it to a
	floating point type.
	(vsx_ext_<VSX_EXTRACT_I:VS_scalar>_ufl_<FL_CONV:mode>): Likewise.

[gcc/testsuite]
2016-12-09  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* gcc/testsuite/gcc.target/powerpc/vec-extract.h: If DO_TRACE is
	defined, add tracing of the various extracts to stderr.  Add
	support for tests that convert the result to another type.
	* gcc/testsuite/gcc.target/powerpc/vec-extract-v2df.c: Likewise.
	* gcc/testsuite/gcc.target/powerpc/vec-extract-v4sf.c: Likewise.
	* gcc/testsuite/gcc.target/powerpc/vec-extract-v4si-df.c: Add new
	tests that do an extract and then convert the values double.
	* gcc/testsuite/gcc.target/powerpc/vec-extract-v4siu-df.c: Likewise.
	* gcc/testsuite/gcc.target/powerpc/vec-extract-v16qiu-df.c: Likewise.
	* gcc/testsuite/gcc.target/powerpc/vec-extract-v16qi-df.c: Likewise.
	* gcc/testsuite/gcc.target/powerpc/vec-extract-v8hiu-df.c: Likewise.
	* gcc/testsuite/gcc.target/powerpc/vec-extract-v8hi-df.c: Likewise.
	* gcc/testsuite/gcc.target/powerpc/vec-extract.h: Likewise.
	* gcc.target/powerpc/p9-extract-1.c: Update test to check for
	VEXTU{B,H,W}{L,R}X instructions being generated by default instead
	of VEXTRACTU{B,H} and XXEXTRACTUW.
	* gcc.target/powerpc/p9-extract-3.c: New test for combination of
	vec_extract and convert to floating point.


-- 
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.vnet.ibm.com, phone: +1 (978) 899-4797

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