This is the mail archive of the mailing list for the GCC project.

Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

Re: [PATCH, rs6000] Fix PR target/71733, ICE with -mcpu=power9 -mno-vsx

On 7/21/16 3:26 AM, Alan Modra wrote:
On Wed, Jul 20, 2016 at 08:51:21PM -0500, Peter Bergner wrote:
This still doesn't answer David's question about what will happen if
we generate this pattern (or one of the older VSX reg+reg patterns)
when we are NOT using -mno-vsx.  In those cases, quad_address_p and
mode_supports_vsx_dform_quad will return true and it seems like
we'll go ahead and generate these reg+offset addresses when they're
not legal for these patterns.

The question doesn't make a great deal of sense.  altivec_mov* and
vsx_mov* have mutually exclusive insn predicates, and at the RTL level
they all look the same.  So even if you did generate the "wrong"
insn RTL, the right one would match.  For example, if you generated
RTL using altivec_mov with -mvsx, vsx_mov would match it, *not*

Ah, so you're saying we'll never generate those patterns (modulo thru
builtins which already force reg+reg addressing), so this isn't a
problem?  Well that answers our question then.  Thanks!


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]