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Re: [patch,avr] minor tweaks for 8-bit operations


On 14.07.2016 05:55, Senthil Kumar Selvaraj wrote:

Georg-Johann Lay writes:

This patch contains some unrelated tweaks

[...]

- Some patterns that match situations with zero_extend that can be performed
with less instructions / register pressure.

From my (admittedly limited) attempts at code size benchmarking, this
one will help a lot I think, considering ints are used everywhere and
they end up always taking 2 regs, even when one would do. Do you have any numbers on the code size improvement this provides?

Regards
Senthil


No, I usually propose such patches when I am coming across respective situation in generated asm or in a dump file and it's clear that the change won't reduce performance loss in other places. My expectations on the overall gains are low, in particular if some subreg-lowering already split from one HI to two QI so that there is no zero_extend any more that could be caught.

For the QImoe plus, and, ior with const_int it might pay to add a "d" clobber if the register ends up in "l" regs. The compiler sometimes reloads the whole stuff into d-regs, i.e. instead of

  LDI R20, -42
  ADD R10, R20

we get

  MOV R20, R10
  ADD R20, -42
  MOV R10, R20

I even came across situations where reload reloads the const_int to a "l" register which might cost up to 4 instructions for the constant alone!

Johann



- comparing HI against -1

Ok for trunk?

Johann


gcc/
	Minor tweaks for QImode.

	* config/avr/predicates.md (const_m255_to_m1_operand): New.
	* config/avr/constraints.md (Cn8, Ca1, Co1, Yx2): New constraints.
	* config/avr/avr.md (add<mode>3) <ALL1>: Make "r,0,r" more
	expensive.
	(*cmphi.zero-extend.0, *cmphi.zero-extend.1)
	(*usum_widenqihi3, *udiff_widenqihi3)
	(*addhi3_zero_extend.const): New combiner insns.
	(andqi3, iorqi3): Provide "l" (NO_LD_REGS) alternative if
	just 1 bit is affected.
	* config/avr/avr.c (avr_out_bitop) <QImode>: Don't access xop[3].
	(avr_out_compare) [EQ,NE]: Tweak comparing d-regs against -1.


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