This is the mail archive of the mailing list for the GCC project.

Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

[PATCH], PR 71805, Fix PowerPC ISA 3.0 xxperm/xxpermr usage

When I initially implemented the xxperm support in the ISA 3.0 extensions, I
misread the manual.  The xxperm (and xxpermr) instruction logically should have
4 arguments, like vperm/vpermr (ouput, 2 inputs that provide the bytes, and the
permute register), but due to encoding issues, it only has 3 VSX arguments.
The output register must be the same as the second input register.  However, I
misread the manual as saying that output be the same as the first input

The test gcc.dg/vect/pr45752.c sets the parameter tree-reassoc-width=1, which
causes the test to be vectorized.  If you don't override the reassociation
width or set it to 2, the code is not vectorized.  When the code is vectorized,
it generates a lot of permute instructions.  This means, the register allocator
runs out of Altivec registers, and generates several xxperm instructions.

In this patch, I have fixed the xxperm instructions to expect the second input
argument to be the same as the output argument instead of the first.  I also
fixed the xxpermr instruction, which suffers from the same problem.  I added
the test case, and made it specific to power9, in case the original test case
is changed.

I have done a bootstrap build with no regressions.  Can I install this patch
into both the trunk and GCC 6, which also shows the bug?

2016-07-11  Michael Meissner  <>

	PR target/71805
	* config/rs6000/ (altivec_vperm_<mode>_internal):
	The xxperm and xxpermr instructions require that the 2nd input
	operand overlap with the output operand, and not the 1st.
	(altivec_vperm_v8hiv16qi): Likewise.
	(altivec_vperm_<mode>_uns_internal): Likewise.
	(altivec_vpermr_<mode>_internal): Likewise.
	(vperm_v8hiv4si): Likewise.
	(vperm_v16qiv8hi): Likewise.

2016-07-11  Michael Meissner  <>

	PR target/71805
	* New test.

Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email:, phone: +1 (978) 899-4797

Attachment: pr71805.patch01b
Description: Text document

Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]