[PATCH], Add PowerPC ISA 3.0 vector d-form addressing

[Michael Meissner <meissner at linux dot vnet dot ibm dot com>]

This patch implements the new instructions added in ISA 3.0 (power9) to allow
d-form (register + offset) memory loads and stores to/from vector registers.

I split the previous -mpower9-dform switch to -mpower9-dform-vector and
-mpower9-dform-scalar in case you need to disable one or both forms.  The
vector d-form instructions are more restricted than the scalar instructions in
that they use a 12-bit offset (like the lq/stq instructions that operate on GPR
registers).

Note, -mpower9-dform-vector is not compatible with RELOAD. I believe the
problem is that we are missing some push_reloads, and it winds up with an
invalid memory address that includes another memory address. Given that we plan
to move from RELOAD to LRA, I stopped trying to debug it, and enabled it only
if LRA is used.

Right now, we cannot move to LRA as the default until the performance
degradations that LRA causes in the 403.gcc spec bencharmark are fixed:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=69847

With this patch, I enable -mlra if the user did not specify either -mlra or
-mno-lra on the command line, and -mcpu=power9 or -mpower9-dform-vector were
used. I also enabled -mvsx-timode if LRA was used, which also is a RELOAD
issue, that works with LRA.

I have built the spec 2006 CPU benchmarks with this option, and all bencmarks
generate vector d-form instructions (mcf only generates stores, not loads).

This patch bootstraps fine on a little endian Power8 compiler and has no
regressions. Is it ok to install in the trunk?

How about in the gcc 6.2 branch after a burn-in period.

[gcc]
2016-05-03  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* config/rs6000/rs6000-cpus.def (ISA_3_0_MASKS_SERVER): Make -mlra
	an option mask instead of setting a separate word.  Add -mlra and
	-mvsx-timode as defaults for power9. Split -mpower9-dform into
	-mpower9-dform-scalar and -mpower9-dform-vector. Add support for
	ISA 3.0 vector d-form instructions. Set -mlra by default if
	-mpower9-dform-vector. Set -mvsx-timode if -mlra. Add more debug
	printouts. If we have ISA 3.0 d-form vector instructions use them
	for the epilog and prolog. Add wO constraint for ISA 3.0 vector
	d-form instructions. Rewrite quad memory support to support both
	lq/stq for GPRs and ISA 3.0 vector d-forms for vector registers.
	Delete p9_vecload_<mode> and p9_vecstore_<mode> in favor of
	folding the ISA 3.0 endian load/store into the general mov<mode>
	insns.
	(POWERPC_MASKS): Likewise.
	* config/rs6000/rs6000.opt (-mlra): Likewise.
	(-mpower9-dform): Likewise.
	(-mpower9-dform-scalar): Likewise.
	(-mpower9-dform-vector): Likewise.
	* config/rs6000/rs6000.c (RELOAD_REG_QUAD_OFFSET): Likewise.
	(mode_supports_vsx_dform_quad): Likewise.
	(rs6000_debug_addr_mask): Likewise.
	(rs6000_setup_reg_addr_masks): Likewise.
	(rs6000_option_override_internal): Likewise.
	(quad_address_offset_p): Likewise.
	(mem_operand_gpr): Likewise.
	(reg_offset_addressing_ok_p): Likewise.
	(offsettable_ok_by_alignment): Likewise.
	(rs6000_legitimate_offset_address_p): Likewise.
	(legitimate_lo_sum_address_p): Likewise.
	(rs6000_legitimize_address): Likewise.
	(rs6000_legitimize_reload_address): Likewise.
	(rs6000_legitimate_address_p): Likewise.
	(rs6000_secondary_reload_memory): Likewise.
	(rs6000_secondary_reload_inner): Likewise.
	(rs6000_preferred_reload_class): Likewise.
	(rs6000_output_move_128bit): Likewise.
	(rs6000_emit_prologue): Likewise.
	(rs6000_emit_epilogue): Likewise.
	(rs6000_lra_p): Likewise.
	(rs6000_opt_masks): Likewise.
	(rs6000_print_options_internal): Likewise.
	* config/rs6000/constraints.md (wO constraint): Likewise.
	* config/rs6000/predicates.md (quad_memory_operand): Likewise.
	(vsx_quad_dform_memory_operand): Likewise.
	* config/rs6000/rs6000-protos.h (quad_address_p): Likewise.
	* config/rs6000/vsx.md (p9_vecload_<mode>): Likewise.
	(p9_vecstore_<mode>): Likewise.
	(vsx_mov<mode): Likewise.
	(vsx_movti_64bi): Likewise.
	(vsx_movti_32bit): Likewise.
	* doc/invoke.texi (RS/6000 and PowerPC Options): Likewise.
	* doc/md.texi (wO constraint): Likewise.

[gcc/testsuite]
2016-05-03  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* gcc.target/powerpc/dform-1.c: Add -mlra to options.
	* gcc.target/powerpc/dform-2.c: Likewise.
	* gcc.target/powerpc/dform-3.c: New test for ISA 3.0 vector d-form
	instructions.


-- 
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.vnet.ibm.com, phone: +1 (978) 899-4797

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