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[PATCH, i386]: Fix ix86_spill_class condition


Hello!

Based on recent discussion, the attached patch fixes ix86_spill_class
condition. The spills to SSE registers are now enabled for real on
SSE2 target, where inter-unit moves to/from vector registers are
enabled.

Since this is new functionality, the patch can cause some minor
runtime regressions (or unwanted regmove chains), so IMO the beginning
of stage1 is appropriate timing for these kind of changes.

TARGET_GENERAL_REGS_SSE_SPILL flag is enabled by default on all Intel
Core processors, so the change will be picked by SPEC testers and any
problems will soon be detected.

2016-04-27  Uros Bizjak  <ubizjak@gmail.com>

    * config/i386/i386.c (ix86_spill_class): Enable for TARGET_SSE2 when
    inter-unit moves to/from vector registers are enabled.  Do not disable
    for TARGET_MMX.

Patch was bootstrapped and regression tested on x86_64-linux-gnu
{,-m32}, configured with --with-arch=corei7.

Committed to mainline SVN.

Uros.

Index: config/i386/i386.c
===================================================================
--- config/i386/i386.c  (revision 235516)
+++ config/i386/i386.c  (working copy)
@@ -53560,9 +53560,12 @@
 static reg_class_t
 ix86_spill_class (reg_class_t rclass, machine_mode mode)
 {
-  if (TARGET_SSE && TARGET_GENERAL_REGS_SSE_SPILL && ! TARGET_MMX
+  if (TARGET_GENERAL_REGS_SSE_SPILL
+      && TARGET_SSE2
+      && TARGET_INTER_UNIT_MOVES_TO_VEC
+      && TARGET_INTER_UNIT_MOVES_FROM_VEC
       && (mode == SImode || (TARGET_64BIT && mode == DImode))
-      && rclass != NO_REGS && INTEGER_CLASS_P (rclass))
+      && INTEGER_CLASS_P (rclass))
     return ALL_SSE_REGS;
   return NO_REGS;
 }


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