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On Thu, Apr 21, 2016 at 9:42 AM, Uros Bizjak <ubizjak@gmail.com> wrote: > On Thu, Apr 21, 2016 at 9:37 AM, Uros Bizjak <ubizjak@gmail.com> wrote: >> On Wed, Apr 20, 2016 at 9:53 PM, H.J. Lu <hongjiu.lu@intel.com> wrote: >>> Since all 1s in TImode is standard SSE2 constants, all 1s in OImode is >>> standard AVX2 constants and all 1s in XImode is standard AVX512F constants, >>> pass mode to standard_sse_constant_p and standard_sse_constant_opcode >>> to check if all 1s is available for target. >>> >>> Tested on Linux/x86-64. OK for master? >> >> No. >> >> This patch should use "isa" attribute instead of adding even more >> similar patterns. Also, please leave MEM_P checks, the rare C->m move >> can be easily resolved by IRA. > > Actually, register_operand checks are indeed better, please disregard > MEM_P recommendation. So, something like attached untested RFC proto-patch, that lacks wide-int handling. Uros.
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