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[PATCH, i386, AVX-512] Fix for PR target/70453.
- From: Kirill Yukhin <kirill dot yukhin at gmail dot com>
- To: GCC Patches <gcc-patches at gcc dot gnu dot org>
- Cc: Uros Bizjak <ubizjak at gmail dot com>
- Date: Thu, 31 Mar 2016 17:54:01 +0300
- Subject: [PATCH, i386, AVX-512] Fix for PR target/70453.
- Authentication-results: sourceware.org; auth=none
Hello,
Patch in the bottom fixes typo causing PR target/70453.
Boostrapped and regtested on i?86/x86_64.
I'll check it into main trunk and gcc-5-branch.
gcc/
PR target/70453
* config/i386/sse.md (define_mode_attr shuffletype): Fix typo.
gcc/testsuite/
PR target/70453
* gcc.target/i386/pr70453.c: New test.
--
Thanks, K
commit 06a60a6aa22b24962b315de1f07cc75b074e47d2
Author: Kirill Yukhin <kirill.yukhin@intel.com>
Date: Wed Mar 30 17:43:12 2016 +0300
AVX-512. Fix typo in <shuffletype> mode attribute.
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 44141ea..5fd650f 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -493,7 +493,7 @@
[(V16SF "f") (V16SI "i") (V8DF "f") (V8DI "i")
(V8SF "f") (V8SI "i") (V4DF "f") (V4DI "i")
(V4SF "f") (V4SI "i") (V2DF "f") (V2DI "i")
- (V32QI "i") (V16HI "u") (V16QI "i") (V8HI "i")
+ (V32QI "i") (V16HI "i") (V16QI "i") (V8HI "i")
(V64QI "i") (V1TI "i") (V2TI "i")])
(define_mode_attr ssequartermode
diff --git a/gcc/testsuite/gcc.target/i386/pr70453.c b/gcc/testsuite/gcc.target/i386/pr70453.c
new file mode 100755
index 0000000..2ff1fbb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr70453.c
@@ -0,0 +1,18 @@
+/* PR target/70453 */
+/* { dg-do assemble { target { lp64 } } } */
+/* { dg-require-effective-target avx512vbmi } */
+/* { dg-options "-Og -fschedule-insns -mavx512vbmi" } */
+
+
+typedef char v64u8 __attribute__ ((vector_size (64)));
+typedef short v64u16 __attribute__ ((vector_size (64)));
+typedef __int128 v64u128 __attribute__ ((vector_size (64)));
+
+int
+foo(v64u8 v64u8_0, v64u16 v64u16_0, v64u128 v64u128_0)
+{
+ v64u128_0 /= (v64u128){ v64u8_0[28] } | 0x1424171b0c;
+ v64u8_0 %= (v64u8){ v64u16_0[25], v64u128_0[1]} ;
+ v64u128_0 %= (v64u128){ v64u16_0[8] };
+ return v64u8_0[0] + v64u8_0[1] + v64u16_0[0] + v64u128_0[0];
+}