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Re: [PATCH][AArch64] Replace insn to zero up DF register
- From: Wilco Dijkstra <Wilco dot Dijkstra at arm dot com>
- To: Evandro Menezes <e dot menezes at samsung dot com>
- Cc: "gcc-patches at gcc dot gnu dot org" <gcc-patches at gcc dot gnu dot org>, nd <nd at arm dot com>, Marcus Shawcroft <Marcus dot Shawcroft at arm dot com>, Kyrylo Tkachov <Kyrylo dot Tkachov at arm dot com>, James Greenhalgh <James dot Greenhalgh at arm dot com>
- Date: Fri, 26 Feb 2016 12:37:33 +0000
- Subject: Re: [PATCH][AArch64] Replace insn to zero up DF register
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Evandro Menezes <e.menezes@samsung.com> wrote:
>
> I have a question though: is it necessary to add the "fp" and "simd"
> attributes to both movsf_aarch64 and movdf_aarch64 as well?
You need at least the "simd" attribute, but providing "fp" as well is clearer
(in principle the TARGET_FLOAT check in the pattern condition is
redundant as a result, but the movhf and movtf patterns already do both).
Also you want to use the smallest possible SIMD size as these are
scalar operations and some microarchitectures execute 64-bit operations
more efficiently than 128-bit ones, so:
mov\\t%0.h[0], %w1
+ movi\\t%0.4h, #0
umov\\t%w0, %1.h[0]
fmov\\t%s0, %w1
+ movi\\t%0.2s, #0
fmov\\t%w0, %s1
With those changes it should be ready for commit once you get the OK from James/Marcus.
Wilco