Re: [PATCH] Fix memory alignment on AVX512VL masked floating point stores (PR target/69198)

["H.J. Lu" <hjl dot tools at gmail dot com>]

On Fri, Jan 8, 2016 at 12:35 PM, Jakub Jelinek <jakub@redhat.com> wrote:
> On Fri, Jan 08, 2016 at 12:28:43PM -0800, H.J. Lu wrote:
>> gcc.target/i386/avx512vl-vmovapd-1.c has
>>
>> ---
>> include <immintrin.h>
>>
>> double *p;
>> volatile __m256d yy, y2;
>> volatile __m128d xx, x2;
>> volatile __mmask8 m;
>>
>> void extern
>> avx512vl_test (void)
>> {
>>   yy = _mm256_mask_mov_pd (yy, m, y2);
>>   xx = _mm_mask_mov_pd (xx, m, x2);
>>
>>   yy = _mm256_maskz_mov_pd (m, y2);
>>   xx = _mm_maskz_mov_pd (m, x2);
>>
>>   yy = _mm256_mask_load_pd (yy, m, p);
>>   xx = _mm_mask_load_pd (xx, m, p);
>>
>>   yy = _mm256_maskz_load_pd (m, p);
>>   xx = _mm_maskz_load_pd (m, p);
>>
>>   _mm256_mask_store_pd (p, m, yy);
>>   _mm_mask_store_pd (p, m, xx);
>> }
>> ---
>>
>> 'p' is misaligned.
>
> p is not misaligned, it has just unknown alignment.

And it may be 8 byte aligned.

>> Why should we change its alignment?
>
> Because the uses of these intrinsics implies the memory is aligned.
> The masked loads also imply aligned memory and has been giving that
> alignment for quite some time, non-masked _mm_store_pd/_mm256_store_pd,
> or even masked _mm512_store_pd as well, just these two (and s/pd/ps/)
> not by a mistake.
> If the memory is not aligned, you'd be using _mm256_mask_storeu_p[ds]
> or _mm_mask_storeu_p[ds] instead.
>

I think the testcase is wrong.  `p' should point to the properly
aligned memory in this case.  If the alignment is unknown,
unaligned intrinsics should be used.


-- 
H.J.