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[PR68432 01/22][ARM] Remove operand dependency from "type" attribute
- From: Richard Sandiford <richard dot sandiford at arm dot com>
- To: gcc-patches at gcc dot gnu dot org
- Cc: nickc at redhat dot com, richard dot earnshaw at arm dot com, ramana dot radhakrishnan at arm dot com, kyrylo dot tkachov at arm dot com
- Date: Wed, 25 Nov 2015 12:21:48 +0000
- Subject: [PR68432 01/22][ARM] Remove operand dependency from "type" attribute
- Authentication-results: sourceware.org; auth=none
- References: <874mgajmo9 dot fsf at e105548-lin dot cambridge dot arm dot com>
The "enabled" attribute is supposed to be an invariant property of an
alternative and shouldn't depend on having access to a particular insn.
Although I think ARM honours that, it's not really enforceable at
compile time because "enabled" depends on "type", which in turn depends
on match_operand. This patch removes the type->match_operand dependency
by splitting alternatives where necessary. This is needed for the fix to
PR 68432.
Tested as described in the covering note.
gcc/
* config/arm/arm.md (*arm_addsi3): Split register+immediate
alternatives and make "type" a constant property of the
alternative number.
(*addsi3_carryin_shift_<optab>): Likewise.
(*subsi3_carryin_shift): Likewise.
(*rsbsi3_carryin_shift): Likewise.
(andsi_not_shiftsi_si): Likewise.
(andsi_not_shiftsi_si_scc_no_reuse): Likewise.
(andsi_not_shiftsi_si_scc): Likewise.
(*movhi_insn_arch4): Likewise.
(*arm_cmpsi_negshiftsi_si): Likewise.
(*movsicc_insn): Likewise.
(*cond_move): Likewise.
(*if_plus_move): Likewise.
(*if_move_plus): Likewise.
(*if_arith_move): Likewise.
(*if_move_arith): Likewise.
(*if_shift_move): Likewise.
(*if_move_shift): Likewise.
(*if_shift_shift): Likewise.
* config/arm/thumb2.md (*thumb2_movsicc_insn): Likewise.
(*thumb2_addsi_short): Likewise.
(thumb2_addsi3_compare0): Likewise.
(*thumb2_addsi3_compare0_scratch): Likewise.
(*thumb2_shiftsi3_short): Make "type" a constant property of the
alternative number.
* config/arm/neon.md (neon_vc<cmp_op><mode>_insn): Likewise.
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 5782b35..40666b4 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -574,9 +574,9 @@
;; (plus (reg rN) (reg sp)) into (reg rN). In this case reload will
;; put the duplicated register first, and not try the commutative version.
(define_insn_and_split "*arm_addsi3"
- [(set (match_operand:SI 0 "s_register_operand" "=rk,l,l ,l ,r ,k ,r,r ,k ,r ,k,k,r ,k ,r")
- (plus:SI (match_operand:SI 1 "s_register_operand" "%0 ,l,0 ,l ,rk,k ,r,rk,k ,rk,k,r,rk,k ,rk")
- (match_operand:SI 2 "reg_or_int_operand" "rk ,l,Py,Pd,rI,rI,k,Pj,Pj,L ,L,L,PJ,PJ,?n")))]
+ [(set (match_operand:SI 0 "s_register_operand" "=rk,l,l ,l ,r ,r ,k,k,r,r ,k ,r ,k,k,r ,k ,r")
+ (plus:SI (match_operand:SI 1 "s_register_operand" "%0 ,l,0 ,l ,rk,rk,k,k,r,rk,k ,rk,k,r,rk,k ,rk")
+ (match_operand:SI 2 "reg_or_int_operand" "rk ,l,Py,Pd,r, I, r,I,k,Pj,Pj,L ,L,L,PJ,PJ,?n")))]
"TARGET_32BIT"
"@
add%?\\t%0, %0, %2
@@ -585,6 +585,8 @@
add%?\\t%0, %1, %2
add%?\\t%0, %1, %2
add%?\\t%0, %1, %2
+ add%?\\t%0, %1, %2
+ add%?\\t%0, %1, %2
add%?\\t%0, %2, %1
addw%?\\t%0, %1, %2
addw%?\\t%0, %1, %2
@@ -605,13 +607,11 @@
operands[1], 0);
DONE;
"
- [(set_attr "length" "2,4,4,4,4,4,4,4,4,4,4,4,4,4,16")
+ [(set_attr "length" "2,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,16")
(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "yes,yes,yes,yes,no,no,no,no,no,no,no,no,no,no,no")
- (set_attr "arch" "t2,t2,t2,t2,*,*,*,t2,t2,*,*,a,t2,t2,*")
- (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
- (const_string "alu_imm")
- (const_string "alu_sreg")))
+ (set_attr "predicable_short_it" "yes,yes,yes,yes,no,no,no,no,no,no,no,no,no,no,no,no,no")
+ (set_attr "arch" "t2,t2,t2,t2,*,*,*,*,*,t2,t2,*,*,a,t2,t2,*")
+ (set_attr "type" "alu_sreg,alu_sreg,alu_imm,alu_imm,alu_sreg,alu_imm,alu_sreg,alu_imm,alu_sreg,alu_imm,alu_imm,alu_imm,alu_imm,alu_imm,alu_imm,alu_imm,alu_imm")
]
)
@@ -835,21 +835,19 @@
)
(define_insn "*addsi3_carryin_shift_<optab>"
- [(set (match_operand:SI 0 "s_register_operand" "=r")
+ [(set (match_operand:SI 0 "s_register_operand" "=r,r")
(plus:SI (plus:SI
(match_operator:SI 2 "shift_operator"
- [(match_operand:SI 3 "s_register_operand" "r")
- (match_operand:SI 4 "reg_or_int_operand" "rM")])
- (match_operand:SI 1 "s_register_operand" "r"))
+ [(match_operand:SI 3 "s_register_operand" "r,r")
+ (match_operand:SI 4 "reg_or_int_operand" "r,M")])
+ (match_operand:SI 1 "s_register_operand" "r,r"))
(LTUGEU:SI (reg:<cnb> CC_REGNUM) (const_int 0))))]
"TARGET_32BIT"
"adc%?\\t%0, %1, %3%S2"
[(set_attr "conds" "use")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
- (set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "")
- (const_string "alu_shift_imm")
- (const_string "alu_shift_reg")))]
+ (set_attr "type" "alu_shift_reg,alu_shift_imm")]
)
(define_insn "*addsi3_carryin_clobercc_<optab>"
@@ -920,37 +918,33 @@
)
(define_insn "*subsi3_carryin_shift"
- [(set (match_operand:SI 0 "s_register_operand" "=r")
+ [(set (match_operand:SI 0 "s_register_operand" "=r,r")
(minus:SI (minus:SI
- (match_operand:SI 1 "s_register_operand" "r")
+ (match_operand:SI 1 "s_register_operand" "r,r")
(match_operator:SI 2 "shift_operator"
- [(match_operand:SI 3 "s_register_operand" "r")
- (match_operand:SI 4 "reg_or_int_operand" "rM")]))
+ [(match_operand:SI 3 "s_register_operand" "r,r")
+ (match_operand:SI 4 "reg_or_int_operand" "r,M")]))
(ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
"TARGET_32BIT"
"sbc%?\\t%0, %1, %3%S2"
[(set_attr "conds" "use")
(set_attr "predicable" "yes")
- (set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "")
- (const_string "alu_shift_imm")
- (const_string "alu_shift_reg")))]
+ (set_attr "type" "alu_shift_reg,alu_shift_imm")]
)
(define_insn "*rsbsi3_carryin_shift"
- [(set (match_operand:SI 0 "s_register_operand" "=r")
+ [(set (match_operand:SI 0 "s_register_operand" "=r,r")
(minus:SI (minus:SI
(match_operator:SI 2 "shift_operator"
- [(match_operand:SI 3 "s_register_operand" "r")
- (match_operand:SI 4 "reg_or_int_operand" "rM")])
- (match_operand:SI 1 "s_register_operand" "r"))
+ [(match_operand:SI 3 "s_register_operand" "r,r")
+ (match_operand:SI 4 "reg_or_int_operand" "r,M")])
+ (match_operand:SI 1 "s_register_operand" "r,r"))
(ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
"TARGET_ARM"
"rsc%?\\t%0, %1, %3%S2"
[(set_attr "conds" "use")
(set_attr "predicable" "yes")
- (set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "")
- (const_string "alu_shift_imm")
- (const_string "alu_shift_reg")))]
+ (set_attr "type" "alu_shift_reg,alu_shift_imm")]
)
; transform ((x << y) - 1) to ~(~(x-1) << y) Where X is a constant.
@@ -2772,18 +2766,16 @@
)
(define_insn "andsi_not_shiftsi_si"
- [(set (match_operand:SI 0 "s_register_operand" "=r")
+ [(set (match_operand:SI 0 "s_register_operand" "=r,r")
(and:SI (not:SI (match_operator:SI 4 "shift_operator"
- [(match_operand:SI 2 "s_register_operand" "r")
- (match_operand:SI 3 "arm_rhs_operand" "rM")]))
- (match_operand:SI 1 "s_register_operand" "r")))]
+ [(match_operand:SI 2 "s_register_operand" "r,r")
+ (match_operand:SI 3 "arm_rhs_operand" "r,M")]))
+ (match_operand:SI 1 "s_register_operand" "r,r")))]
"TARGET_ARM"
"bic%?\\t%0, %1, %2%S4"
[(set_attr "predicable" "yes")
(set_attr "shift" "2")
- (set (attr "type") (if_then_else (match_operand 3 "const_int_operand" "")
- (const_string "logic_shift_imm")
- (const_string "logic_shift_reg")))]
+ (set_attr "type" "logic_shift_reg,logic_shift_imm")]
)
;; Shifted bics pattern used to set up CC status register and not reusing
@@ -2793,20 +2785,18 @@
[(set (reg:CC_NOOV CC_REGNUM)
(compare:CC_NOOV
(and:SI (not:SI (match_operator:SI 0 "shift_operator"
- [(match_operand:SI 1 "s_register_operand" "r")
- (match_operand:SI 2 "arm_rhs_operand" "rM")]))
- (match_operand:SI 3 "s_register_operand" "r"))
+ [(match_operand:SI 1 "s_register_operand" "r,r")
+ (match_operand:SI 2 "arm_rhs_operand" "r,M")]))
+ (match_operand:SI 3 "s_register_operand" "r,r"))
(const_int 0)))
- (clobber (match_scratch:SI 4 "=r"))]
+ (clobber (match_scratch:SI 4 "=r,r"))]
"TARGET_ARM || (TARGET_THUMB2 && CONST_INT_P (operands[2]))"
"bics%?\\t%4, %3, %1%S0"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "conds" "set")
(set_attr "shift" "1")
- (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
- (const_string "logic_shift_imm")
- (const_string "logic_shift_reg")))]
+ (set_attr "type" "logic_shift_reg,logic_shift_imm")]
)
;; Same as andsi_not_shiftsi_si_scc_no_reuse, but the bics result is also
@@ -2815,11 +2805,11 @@
[(parallel [(set (reg:CC_NOOV CC_REGNUM)
(compare:CC_NOOV
(and:SI (not:SI (match_operator:SI 0 "shift_operator"
- [(match_operand:SI 1 "s_register_operand" "r")
- (match_operand:SI 2 "arm_rhs_operand" "rM")]))
- (match_operand:SI 3 "s_register_operand" "r"))
+ [(match_operand:SI 1 "s_register_operand" "r,r")
+ (match_operand:SI 2 "arm_rhs_operand" "r,M")]))
+ (match_operand:SI 3 "s_register_operand" "r,r"))
(const_int 0)))
- (set (match_operand:SI 4 "s_register_operand" "=r")
+ (set (match_operand:SI 4 "s_register_operand" "=r,r")
(and:SI (not:SI (match_op_dup 0
[(match_dup 1)
(match_dup 2)]))
@@ -2830,9 +2820,7 @@
(set_attr "predicable_short_it" "no")
(set_attr "conds" "set")
(set_attr "shift" "1")
- (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
- (const_string "logic_shift_imm")
- (const_string "logic_shift_reg")))]
+ (set_attr "type" "logic_shift_reg,logic_shift_imm")]
)
(define_insn "*andsi_notsi_si_compare0"
@@ -6343,30 +6331,24 @@
;; Pattern to recognize insn generated default case above
(define_insn "*movhi_insn_arch4"
- [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m,r")
- (match_operand:HI 1 "general_operand" "rIk,K,n,r,mi"))]
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,r,m,r")
+ (match_operand:HI 1 "general_operand" "rk,I,K,n,r,mi"))]
"TARGET_ARM
&& arm_arch4
&& (register_operand (operands[0], HImode)
|| register_operand (operands[1], HImode))"
"@
mov%?\\t%0, %1\\t%@ movhi
+ mov%?\\t%0, %1\\t%@ movhi
mvn%?\\t%0, #%B1\\t%@ movhi
movw%?\\t%0, %L1\\t%@ movhi
strh%?\\t%1, %0\\t%@ movhi
ldrh%?\\t%0, %1\\t%@ movhi"
[(set_attr "predicable" "yes")
- (set_attr "pool_range" "*,*,*,*,256")
- (set_attr "neg_pool_range" "*,*,*,*,244")
- (set_attr "arch" "*,*,v6t2,*,*")
- (set_attr_alternative "type"
- [(if_then_else (match_operand 1 "const_int_operand" "")
- (const_string "mov_imm" )
- (const_string "mov_reg"))
- (const_string "mvn_imm")
- (const_string "mov_imm")
- (const_string "store1")
- (const_string "load1")])]
+ (set_attr "pool_range" "*,*,*,*,*,256")
+ (set_attr "neg_pool_range" "*,*,*,*,*,244")
+ (set_attr "arch" "*,*,*,v6t2,*,*")
+ (set_attr "type" "mov_reg,mov_imm,mvn_imm,mov_imm,store1,load1")]
)
(define_insn "*movhi_bytes"
@@ -6964,15 +6946,13 @@
[(set (reg:CC_Z CC_REGNUM)
(compare:CC_Z
(neg:SI (match_operator:SI 1 "shift_operator"
- [(match_operand:SI 2 "s_register_operand" "r")
- (match_operand:SI 3 "reg_or_int_operand" "rM")]))
- (match_operand:SI 0 "s_register_operand" "r")))]
+ [(match_operand:SI 2 "s_register_operand" "r,r")
+ (match_operand:SI 3 "reg_or_int_operand" "r,M")]))
+ (match_operand:SI 0 "s_register_operand" "r,r")))]
"TARGET_ARM"
"cmn%?\\t%0, %2%S1"
[(set_attr "conds" "set")
- (set (attr "type") (if_then_else (match_operand 3 "const_int_operand" "")
- (const_string "alus_shift_imm")
- (const_string "alus_shift_reg")))
+ (set_attr "type" "alus_shift_reg,alus_shift_imm")
(set_attr "predicable" "yes")]
)
@@ -7489,17 +7469,19 @@
)
(define_insn_and_split "*movsicc_insn"
- [(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r,r,r,r,r")
+ [(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r,r,r,r,r,r,r")
(if_then_else:SI
(match_operator 3 "arm_comparison_operator"
[(match_operand 4 "cc_register" "") (const_int 0)])
- (match_operand:SI 1 "arm_not_operand" "0,0,rI,K,rI,rI,K,K")
- (match_operand:SI 2 "arm_not_operand" "rI,K,0,0,rI,K,rI,K")))]
+ (match_operand:SI 1 "arm_not_operand" "0,0,0,r,I,K,rI,rI,K,K")
+ (match_operand:SI 2 "arm_not_operand" "r,I,K,0,0,0,rI,K,rI,K")))]
"TARGET_ARM"
"@
mov%D3\\t%0, %2
+ mov%D3\\t%0, %2
mvn%D3\\t%0, #%B2
mov%d3\\t%0, %1
+ mov%d3\\t%0, %1
mvn%d3\\t%0, #%B1
#
#
@@ -7536,21 +7518,9 @@
gen_rtx_SET (operands[0], operands[2])));
DONE;
}
- [(set_attr "length" "4,4,4,4,8,8,8,8")
+ [(set_attr "length" "4,4,4,4,4,4,8,8,8,8")
(set_attr "conds" "use")
- (set_attr_alternative "type"
- [(if_then_else (match_operand 2 "const_int_operand" "")
- (const_string "mov_imm")
- (const_string "mov_reg"))
- (const_string "mvn_imm")
- (if_then_else (match_operand 1 "const_int_operand" "")
- (const_string "mov_imm")
- (const_string "mov_reg"))
- (const_string "mvn_imm")
- (const_string "multiple")
- (const_string "multiple")
- (const_string "multiple")
- (const_string "multiple")])]
+ (set_attr "type" "mov_reg,mov_imm,mvn_imm,mov_reg,mov_imm,mvn_imm,multiple,multiple,multiple,multiple")]
)
(define_insn "*movsfcc_soft_insn"
@@ -8713,39 +8683,32 @@
")
(define_insn "*cond_move"
- [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
+ [(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r,r")
(if_then_else:SI (match_operator 3 "equality_operator"
[(match_operator 4 "arm_comparison_operator"
[(match_operand 5 "cc_register" "") (const_int 0)])
(const_int 0)])
- (match_operand:SI 1 "arm_rhs_operand" "0,rI,?rI")
- (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))]
+ (match_operand:SI 1 "arm_rhs_operand" "0,0,r,I,?rI")
+ (match_operand:SI 2 "arm_rhs_operand" "r,I,0,0,rI")))]
"TARGET_ARM"
"*
if (GET_CODE (operands[3]) == NE)
{
- if (which_alternative != 1)
+ if (which_alternative != 2 && which_alternative != 3)
output_asm_insn (\"mov%D4\\t%0, %2\", operands);
- if (which_alternative != 0)
+ if (which_alternative != 0 && which_alternative != 1)
output_asm_insn (\"mov%d4\\t%0, %1\", operands);
return \"\";
}
- if (which_alternative != 0)
+ if (which_alternative != 0 && which_alternative != 1)
output_asm_insn (\"mov%D4\\t%0, %1\", operands);
- if (which_alternative != 1)
+ if (which_alternative != 2 && which_alternative != 3)
output_asm_insn (\"mov%d4\\t%0, %2\", operands);
return \"\";
"
[(set_attr "conds" "use")
- (set_attr_alternative "type"
- [(if_then_else (match_operand 2 "const_int_operand" "")
- (const_string "mov_imm")
- (const_string "mov_reg"))
- (if_then_else (match_operand 1 "const_int_operand" "")
- (const_string "mov_imm")
- (const_string "mov_reg"))
- (const_string "multiple")])
- (set_attr "length" "4,4,8")]
+ (set_attr "type" "mov_reg,mov_imm,mov_reg,mov_imm,multiple")
+ (set_attr "length" "4,4,4,4,8")]
)
(define_insn "*cond_arith"
@@ -9515,29 +9478,24 @@
)
(define_insn "*if_plus_move"
- [(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r")
+ [(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r,r")
(if_then_else:SI
(match_operator 4 "arm_comparison_operator"
[(match_operand 5 "cc_register" "") (const_int 0)])
(plus:SI
- (match_operand:SI 2 "s_register_operand" "r,r,r,r")
- (match_operand:SI 3 "arm_add_operand" "rI,L,rI,L"))
- (match_operand:SI 1 "arm_rhs_operand" "0,0,?rI,?rI")))]
+ (match_operand:SI 2 "s_register_operand" "r,r,r,r,r")
+ (match_operand:SI 3 "arm_add_operand" "r,I,L,rI,L"))
+ (match_operand:SI 1 "arm_rhs_operand" "0,0,0,?rI,?rI")))]
"TARGET_ARM"
"@
add%d4\\t%0, %2, %3
+ add%d4\\t%0, %2, %3
sub%d4\\t%0, %2, #%n3
add%d4\\t%0, %2, %3\;mov%D4\\t%0, %1
sub%d4\\t%0, %2, #%n3\;mov%D4\\t%0, %1"
[(set_attr "conds" "use")
- (set_attr "length" "4,4,8,8")
- (set_attr_alternative "type"
- [(if_then_else (match_operand 3 "const_int_operand" "")
- (const_string "alu_imm" )
- (const_string "alu_sreg"))
- (const_string "alu_imm")
- (const_string "multiple")
- (const_string "multiple")])]
+ (set_attr "length" "4,4,4,8,8")
+ (set_attr "type" "alu_sreg,alu_imm,alu_imm,multiple,multiple")]
)
(define_insn "*ifcompare_move_plus"
@@ -9558,29 +9516,24 @@
)
(define_insn "*if_move_plus"
- [(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r")
+ [(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r,r")
(if_then_else:SI
(match_operator 4 "arm_comparison_operator"
[(match_operand 5 "cc_register" "") (const_int 0)])
- (match_operand:SI 1 "arm_rhs_operand" "0,0,?rI,?rI")
+ (match_operand:SI 1 "arm_rhs_operand" "0,0,0,?rI,?rI")
(plus:SI
- (match_operand:SI 2 "s_register_operand" "r,r,r,r")
- (match_operand:SI 3 "arm_add_operand" "rI,L,rI,L"))))]
+ (match_operand:SI 2 "s_register_operand" "r,r,r,r,r")
+ (match_operand:SI 3 "arm_add_operand" "r,I,L,rI,L"))))]
"TARGET_ARM"
"@
add%D4\\t%0, %2, %3
+ add%D4\\t%0, %2, %3
sub%D4\\t%0, %2, #%n3
add%D4\\t%0, %2, %3\;mov%d4\\t%0, %1
sub%D4\\t%0, %2, #%n3\;mov%d4\\t%0, %1"
[(set_attr "conds" "use")
- (set_attr "length" "4,4,8,8")
- (set_attr_alternative "type"
- [(if_then_else (match_operand 3 "const_int_operand" "")
- (const_string "alu_imm" )
- (const_string "alu_sreg"))
- (const_string "alu_imm")
- (const_string "multiple")
- (const_string "multiple")])]
+ (set_attr "length" "4,4,4,8,8")
+ (set_attr "type" "alu_sreg,alu_imm,alu_imm,multiple,multiple")]
)
(define_insn "*ifcompare_arith_arith"
@@ -9662,24 +9615,21 @@
)
(define_insn "*if_arith_move"
- [(set (match_operand:SI 0 "s_register_operand" "=r,r")
+ [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
(if_then_else:SI (match_operator 4 "arm_comparison_operator"
[(match_operand 6 "cc_register" "") (const_int 0)])
(match_operator:SI 5 "shiftable_operator"
- [(match_operand:SI 2 "s_register_operand" "r,r")
- (match_operand:SI 3 "arm_rhs_operand" "rI,rI")])
- (match_operand:SI 1 "arm_rhs_operand" "0,?rI")))]
+ [(match_operand:SI 2 "s_register_operand" "r,r,r")
+ (match_operand:SI 3 "arm_rhs_operand" "r,I,rI")])
+ (match_operand:SI 1 "arm_rhs_operand" "0,0,?rI")))]
"TARGET_ARM"
"@
%I5%d4\\t%0, %2, %3
+ %I5%d4\\t%0, %2, %3
%I5%d4\\t%0, %2, %3\;mov%D4\\t%0, %1"
[(set_attr "conds" "use")
- (set_attr "length" "4,8")
- (set_attr_alternative "type"
- [(if_then_else (match_operand 3 "const_int_operand" "")
- (const_string "alu_shift_imm" )
- (const_string "alu_shift_reg"))
- (const_string "multiple")])]
+ (set_attr "length" "4,4,8")
+ (set_attr "type" "alu_shift_reg,alu_shift_imm,multiple")]
)
(define_insn "*ifcompare_move_arith"
@@ -9726,25 +9676,22 @@
)
(define_insn "*if_move_arith"
- [(set (match_operand:SI 0 "s_register_operand" "=r,r")
+ [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
(if_then_else:SI
(match_operator 4 "arm_comparison_operator"
[(match_operand 6 "cc_register" "") (const_int 0)])
- (match_operand:SI 1 "arm_rhs_operand" "0,?rI")
+ (match_operand:SI 1 "arm_rhs_operand" "0,0,?rI")
(match_operator:SI 5 "shiftable_operator"
- [(match_operand:SI 2 "s_register_operand" "r,r")
- (match_operand:SI 3 "arm_rhs_operand" "rI,rI")])))]
+ [(match_operand:SI 2 "s_register_operand" "r,r,r")
+ (match_operand:SI 3 "arm_rhs_operand" "r,I,rI")])))]
"TARGET_ARM"
"@
%I5%D4\\t%0, %2, %3
+ %I5%D4\\t%0, %2, %3
%I5%D4\\t%0, %2, %3\;mov%d4\\t%0, %1"
[(set_attr "conds" "use")
- (set_attr "length" "4,8")
- (set_attr_alternative "type"
- [(if_then_else (match_operand 3 "const_int_operand" "")
- (const_string "alu_shift_imm" )
- (const_string "alu_shift_reg"))
- (const_string "multiple")])]
+ (set_attr "length" "4,4,8")
+ (set_attr "type" "alu_shift_reg,alu_shift_imm,multiple")]
)
(define_insn "*ifcompare_move_not"
@@ -9835,28 +9782,24 @@
)
(define_insn "*if_shift_move"
- [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
+ [(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r")
(if_then_else:SI
(match_operator 5 "arm_comparison_operator"
[(match_operand 6 "cc_register" "") (const_int 0)])
(match_operator:SI 4 "shift_operator"
- [(match_operand:SI 2 "s_register_operand" "r,r,r")
- (match_operand:SI 3 "arm_rhs_operand" "rM,rM,rM")])
- (match_operand:SI 1 "arm_not_operand" "0,?rI,K")))]
+ [(match_operand:SI 2 "s_register_operand" "r,r,r,r")
+ (match_operand:SI 3 "arm_rhs_operand" "r,M,rM,rM")])
+ (match_operand:SI 1 "arm_not_operand" "0,0,?rI,K")))]
"TARGET_ARM"
"@
mov%d5\\t%0, %2%S4
+ mov%d5\\t%0, %2%S4
mov%D5\\t%0, %1\;mov%d5\\t%0, %2%S4
mvn%D5\\t%0, #%B1\;mov%d5\\t%0, %2%S4"
[(set_attr "conds" "use")
(set_attr "shift" "2")
- (set_attr "length" "4,8,8")
- (set_attr_alternative "type"
- [(if_then_else (match_operand 3 "const_int_operand" "")
- (const_string "mov_shift" )
- (const_string "mov_shift_reg"))
- (const_string "multiple")
- (const_string "multiple")])]
+ (set_attr "length" "4,4,8,8")
+ (set_attr "type" "mov_shift_reg,mov_shift,multiple,multiple")]
)
(define_insn "*ifcompare_move_shift"
@@ -9878,28 +9821,24 @@
)
(define_insn "*if_move_shift"
- [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
+ [(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r")
(if_then_else:SI
(match_operator 5 "arm_comparison_operator"
[(match_operand 6 "cc_register" "") (const_int 0)])
- (match_operand:SI 1 "arm_not_operand" "0,?rI,K")
+ (match_operand:SI 1 "arm_not_operand" "0,0,?rI,K")
(match_operator:SI 4 "shift_operator"
- [(match_operand:SI 2 "s_register_operand" "r,r,r")
- (match_operand:SI 3 "arm_rhs_operand" "rM,rM,rM")])))]
+ [(match_operand:SI 2 "s_register_operand" "r,r,r,r")
+ (match_operand:SI 3 "arm_rhs_operand" "r,M,rM,rM")])))]
"TARGET_ARM"
"@
mov%D5\\t%0, %2%S4
+ mov%D5\\t%0, %2%S4
mov%d5\\t%0, %1\;mov%D5\\t%0, %2%S4
mvn%d5\\t%0, #%B1\;mov%D5\\t%0, %2%S4"
[(set_attr "conds" "use")
(set_attr "shift" "2")
- (set_attr "length" "4,8,8")
- (set_attr_alternative "type"
- [(if_then_else (match_operand 3 "const_int_operand" "")
- (const_string "mov_shift" )
- (const_string "mov_shift_reg"))
- (const_string "multiple")
- (const_string "multiple")])]
+ (set_attr "length" "4,4,8,8")
+ (set_attr "type" "mov_shift_reg,mov_shift,multiple,multiple")]
)
(define_insn "*ifcompare_shift_shift"
@@ -9923,26 +9862,22 @@
)
(define_insn "*if_shift_shift"
- [(set (match_operand:SI 0 "s_register_operand" "=r")
+ [(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r")
(if_then_else:SI
(match_operator 5 "arm_comparison_operator"
[(match_operand 8 "cc_register" "") (const_int 0)])
(match_operator:SI 6 "shift_operator"
- [(match_operand:SI 1 "s_register_operand" "r")
- (match_operand:SI 2 "arm_rhs_operand" "rM")])
+ [(match_operand:SI 1 "s_register_operand" "r,r,r,r")
+ (match_operand:SI 2 "arm_rhs_operand" "r,r,M,M")])
(match_operator:SI 7 "shift_operator"
- [(match_operand:SI 3 "s_register_operand" "r")
- (match_operand:SI 4 "arm_rhs_operand" "rM")])))]
+ [(match_operand:SI 3 "s_register_operand" "r,r,r,r")
+ (match_operand:SI 4 "arm_rhs_operand" "r,M,r,M")])))]
"TARGET_ARM"
"mov%d5\\t%0, %1%S6\;mov%D5\\t%0, %3%S7"
[(set_attr "conds" "use")
(set_attr "shift" "1")
(set_attr "length" "8")
- (set (attr "type") (if_then_else
- (and (match_operand 2 "const_int_operand" "")
- (match_operand 4 "const_int_operand" ""))
- (const_string "mov_shift")
- (const_string "mov_shift_reg")))]
+ (set_attr "type" "mov_shift_reg,mov_shift_reg,mov_shift_reg,mov_shift")]
)
(define_insn "*ifcompare_not_arith"
diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
index 62fb6da..a346927 100644
--- a/gcc/config/arm/neon.md
+++ b/gcc/config/arm/neon.md
@@ -2196,10 +2196,7 @@
output_asm_insn (pattern, operands);
return "";
}
- [(set (attr "type")
- (if_then_else (match_operand 2 "zero_operand")
- (const_string "neon_compare_zero<q>")
- (const_string "neon_compare<q>")))]
+ [(set_attr "type" "neon_compare<q>,neon_compare_zero<q>")]
)
(define_insn "neon_vc<cmp_op_unsp><mode>_insn_unspec"
diff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md
index a724752..c7beda4 100644
--- a/gcc/config/arm/thumb2.md
+++ b/gcc/config/arm/thumb2.md
@@ -478,19 +478,23 @@
)
(define_insn_and_split "*thumb2_movsicc_insn"
- [(set (match_operand:SI 0 "s_register_operand" "=l,l,r,r,r,r,r,r,r,r,r,r")
+ [(set (match_operand:SI 0 "s_register_operand" "=l,l,l,l,r,r,r,r,r,r,r,r,r,r,r,r")
(if_then_else:SI
(match_operator 3 "arm_comparison_operator"
[(match_operand 4 "cc_register" "") (const_int 0)])
- (match_operand:SI 1 "arm_not_operand" "0 ,lPy,0 ,0,rI,K,I ,r,rI,K ,K,r")
- (match_operand:SI 2 "arm_not_operand" "lPy,0 ,rI,K,0 ,0,rI,I,K ,rI,K,r")))]
+ (match_operand:SI 1 "arm_not_operand" "0,0 ,l,Py,0,0,0,r,I,K,I ,r,rI,K ,K,r")
+ (match_operand:SI 2 "arm_not_operand" "l,Py,0,0 ,r,I,K,0,0,0,rI,I,K ,rI,K,r")))]
"TARGET_THUMB2"
"@
it\\t%D3\;mov%D3\\t%0, %2
+ it\\t%D3\;mov%D3\\t%0, %2
+ it\\t%d3\;mov%d3\\t%0, %1
it\\t%d3\;mov%d3\\t%0, %1
it\\t%D3\;mov%D3\\t%0, %2
+ it\\t%D3\;mov%D3\\t%0, %2
it\\t%D3\;mvn%D3\\t%0, #%B2
it\\t%d3\;mov%d3\\t%0, %1
+ it\\t%d3\;mov%d3\\t%0, %1
it\\t%d3\;mvn%d3\\t%0, #%B1
#
#
@@ -530,30 +534,10 @@
gen_rtx_SET (operands[0], operands[2])));
DONE;
}
- [(set_attr "length" "4,4,6,6,6,6,10,8,10,10,10,6")
- (set_attr "enabled_for_depr_it" "yes,yes,no,no,no,no,no,no,no,no,no,yes")
+ [(set_attr "length" "4,4,4,4,6,6,6,6,6,6,10,8,10,10,10,6")
+ (set_attr "enabled_for_depr_it" "yes,yes,yes,yes,no,no,no,no,no,no,no,no,no,no,no,yes")
(set_attr "conds" "use")
- (set_attr_alternative "type"
- [(if_then_else (match_operand 2 "const_int_operand" "")
- (const_string "mov_imm")
- (const_string "mov_reg"))
- (if_then_else (match_operand 1 "const_int_operand" "")
- (const_string "mov_imm")
- (const_string "mov_reg"))
- (if_then_else (match_operand 2 "const_int_operand" "")
- (const_string "mov_imm")
- (const_string "mov_reg"))
- (const_string "mvn_imm")
- (if_then_else (match_operand 1 "const_int_operand" "")
- (const_string "mov_imm")
- (const_string "mov_reg"))
- (const_string "mvn_imm")
- (const_string "multiple")
- (const_string "multiple")
- (const_string "multiple")
- (const_string "multiple")
- (const_string "multiple")
- (const_string "multiple")])]
+ (set_attr "type" "mov_reg,mov_imm,mov_reg,mov_imm,mov_reg,mov_imm,mvn_imm,mov_reg,mov_imm,mvn_imm,multiple,multiple,multiple,multiple,multiple,multiple")]
)
(define_insn "*thumb2_movsfcc_soft_insn"
@@ -1152,9 +1136,7 @@
[(set_attr "predicable" "yes")
(set_attr "shift" "1")
(set_attr "length" "2")
- (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
- (const_string "alu_shift_imm")
- (const_string "alu_shift_reg")))]
+ (set_attr "type" "alu_shift_reg,alu_shift_imm")]
)
(define_insn "*thumb2_mov<mode>_shortim"
@@ -1169,9 +1151,9 @@
)
(define_insn "*thumb2_addsi_short"
- [(set (match_operand:SI 0 "low_register_operand" "=l,l")
- (plus:SI (match_operand:SI 1 "low_register_operand" "l,0")
- (match_operand:SI 2 "low_reg_or_int_operand" "lPt,Ps")))
+ [(set (match_operand:SI 0 "low_register_operand" "=l,l,l")
+ (plus:SI (match_operand:SI 1 "low_register_operand" "l,l,0")
+ (match_operand:SI 2 "low_reg_or_int_operand" "l,Pt,Ps")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_THUMB2 && reload_completed"
"*
@@ -1190,11 +1172,7 @@
"
[(set_attr "predicable" "yes")
(set_attr "length" "2")
- (set_attr_alternative "type"
- [(if_then_else (match_operand 2 "const_int_operand" "")
- (const_string "alu_imm")
- (const_string "alu_sreg"))
- (const_string "alu_imm")])]
+ (set_attr "type" "alu_sreg,alu_imm,alu_imm")]
)
(define_insn "*thumb2_subsi_short"
@@ -1238,10 +1216,10 @@
(define_insn "thumb2_addsi3_compare0"
[(set (reg:CC_NOOV CC_REGNUM)
(compare:CC_NOOV
- (plus:SI (match_operand:SI 1 "s_register_operand" "l, 0, r")
- (match_operand:SI 2 "arm_add_operand" "lPt,Ps,rIL"))
+ (plus:SI (match_operand:SI 1 "s_register_operand" "l,l, 0, r,r")
+ (match_operand:SI 2 "arm_add_operand" "l,Pt,Ps,r,IL"))
(const_int 0)))
- (set (match_operand:SI 0 "s_register_operand" "=l,l,r")
+ (set (match_operand:SI 0 "s_register_operand" "=l,l,l,r,r")
(plus:SI (match_dup 1) (match_dup 2)))]
"TARGET_THUMB2"
"*
@@ -1258,22 +1236,15 @@
return \"adds\\t%0, %1, %2\";
"
[(set_attr "conds" "set")
- (set_attr "length" "2,2,4")
- (set_attr_alternative "type"
- [(if_then_else (match_operand 2 "const_int_operand" "")
- (const_string "alus_imm")
- (const_string "alus_sreg"))
- (const_string "alus_imm")
- (if_then_else (match_operand 2 "const_int_operand" "")
- (const_string "alus_imm")
- (const_string "alus_sreg"))])]
+ (set_attr "length" "2,2,2,4,4")
+ (set_attr "type" "alus_sreg,alus_imm,alus_imm,alus_sreg,alus_imm")]
)
(define_insn "*thumb2_addsi3_compare0_scratch"
[(set (reg:CC_NOOV CC_REGNUM)
(compare:CC_NOOV
- (plus:SI (match_operand:SI 0 "s_register_operand" "l, r")
- (match_operand:SI 1 "arm_add_operand" "lPv,rIL"))
+ (plus:SI (match_operand:SI 0 "s_register_operand" "l,l, r,r")
+ (match_operand:SI 1 "arm_add_operand" "l,Pv,r,IL"))
(const_int 0)))]
"TARGET_THUMB2"
"*
@@ -1290,10 +1261,8 @@
return \"cmn\\t%0, %1\";
"
[(set_attr "conds" "set")
- (set_attr "length" "2,4")
- (set (attr "type") (if_then_else (match_operand 1 "const_int_operand" "")
- (const_string "alus_imm")
- (const_string "alus_sreg")))]
+ (set_attr "length" "2,2,4,4")
+ (set_attr "type" "alus_sreg,alus_imm,alus_sreg,alus_imm")]
)
(define_insn "*thumb2_mulsi_short"