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Re: [Patch 2/2 ARM/AArch64] Add a new Cortex-A53 scheduling model


On Mon, Oct 05, 2015 at 11:07:45AM +0100, Christophe Lyon wrote:
> On 1 October 2015 at 11:41, James Greenhalgh <james.greenhalgh@arm.com> wrote:
> > On Thu, Oct 01, 2015 at 09:33:07AM +0100, Marcus Shawcroft wrote:
> >> On 25/09/15 08:59, James Greenhalgh wrote:
> >> >
> >> > Hi,
> >> >
> >> > This patch introduces a new scheduling model for Cortex-A53.
> >> >
> >> > Bootstrapped and tested on arm-none-linux-gnueabi and aarch64-none-linux-gnu
> >> > and checked with a variety of popular benchmarking and microbenchmarking
> >> > suites to show a benefit.
> >> >
> >> > OK?
> >> >
> >> > Thanks,
> >> > James
> >> >
> >> > ---
> >> > 2015-09-25  James Greenhalgh  <james.greenhalgh@arm.com>
> >> >
> >> >     * config/arm/aarch-common-protos.h
> >> >     (aarch_accumulator_forwarding): New.
> >> >     (aarch_forward_to_shift_is_not_shifted_reg): Likewise.
> >> >     * config/arm/aarch-common.c (aarch_accumulator_forwarding): New.
> >> >     (aarch_forward_to_shift_is_not_shifted_reg): Liekwise.
> >> >     * config/arm/cortex-a53.md: Rewrite.
> >> >
> >>
> >> OK aarch64 with Kyrill's comments fixed.
> >> /M
> >
> > Thanks,
> >
> > I had to rebase this over Evandro's recent patch adding neon_ldp/neon_ldp_q
> > types to the old scheduling model. The rebase was obvious to resolve, and
> > while I was there I also added the neon_stp/neon_stp_q types which were
> > missing.
> >
> > I've attached what I ultimately committed as revision 228324. I messed up
> > fixing the ChangeLog typo before commit, so that is revision 228325.
> >
> 
> Hi James,
> 
> Since this commit I can see
> gcc.target/aarch64/advsimd-intrinsics/vst1_lane.c fail at -O2
> /aci-gcc-fsf/sources/gcc-fsf/gccsrc/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1_lane.c:
> In function 'exec_vst1_lane':
> /aci-gcc-fsf/sources/gcc-fsf/gccsrc/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1_lane.c:96:1:
> internal compiler error: output_operand: invalid %-code
> 0x78f79e output_operand_lossage(char const*, ...)
>         /aci-gcc-fsf/sources/gcc-fsf/gccsrc/gcc/final.c:3417
> 0x7934f3 output_asm_insn(char const*, rtx_def**)
>         /aci-gcc-fsf/sources/gcc-fsf/gccsrc/gcc/final.c:3782
> 0x793d77 final_scan_insn(rtx_insn*, _IO_FILE*, int, int, int*)
>         /aci-gcc-fsf/sources/gcc-fsf/gccsrc/gcc/final.c:3029
> 0x794b3a final(rtx_insn*, _IO_FILE*, int)
>         /aci-gcc-fsf/sources/gcc-fsf/gccsrc/gcc/final.c:2058
> 0x7956fb rest_of_handle_final
>         /aci-gcc-fsf/sources/gcc-fsf/gccsrc/gcc/final.c:4449
> 0x7956fb execute
>         /aci-gcc-fsf/sources/gcc-fsf/gccsrc/gcc/final.c:4524
> Please submit a full bug report,
> 
> on aarch64_be.
> 
> I haven't looked at it in more details though.

Hi Christophe,

Thanks for the report, I'd be surprised if that was to do with the
scheduling model. I can reproduce the failure, and expect that Kugan's
patch at https://gcc.gnu.org/ml/gcc-patches/2015-10/msg00129.html ought
to do the job of fixing the ICE.

Thanks,
James


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