RE: [PATCH 1/4] [MIPS] Add support for MIPS SIMD Architecture (MSA)

[Matthew Fortune <Matthew dot Fortune at imgtec dot com>]

Hi Robert,

I'm taking small steps at this review. I did the first few files as below.
mips-msa.md is next so don't expect the it quickly. I might do that in pieces
too.

No need to post an updated patch until I'm all the way through but I'd
appreciate an explicit ok/done to each point or discussion if you disagree.

>diff --git a/gcc/config/mips/constraints.md b/gcc/config/mips/constraints.md
>index 7d1a8ba..cde0196 100644
>--- a/gcc/config/mips/constraints.md
>+++ b/gcc/config/mips/constraints.md
>@@ -308,6 +308,53 @@ (define_constraint "Yx"
>    "@internal"
>    (match_operand 0 "low_bitmask_operand"))
> 
>+(define_constraint "YI"
>+  "@internal
>+   A replicated vector const in which the replicated is a 10-bit signed value."

replicated value is in the range [-512,511].

>+(define_constraint "Unv5"
>+  "@internal
>+   A replicated vector const in which the replicated value is a negative
>+   integer number in range [-31,0]."

Stick with similar phrasing throughout: replicated value is in the range...

>+  (and (match_code "const_vector")
>+       (match_test "mips_const_vector_same_int_p (op, mode, -31, 0)")))
>+
>+(define_constraint "Uuv5"
>+  "@internal
>+   A replicated vector const in which the replicated value is a positive
>+   integer number in range [0,31]."
>+  (and (match_code "const_vector")
>+       (match_test "mips_const_vector_same_int_p (op, mode, 0, 31)")))

likewise.

>+(define_constraint "Uuv6"
>+  "@internal
>+   A replicated vector const in which the replicated value is an unsigned
>+   6-bit integer number."
>+  (and (match_code "const_vector")
>+       (match_test "mips_const_vector_same_int_p (op, mode, 0, 63)")))

likewise.

>+(define_constraint "Ubv8"
>+  "@internal
>+   A replicated vector const in which the replicated value is an 8-bit byte."

A replicated vector const.

(see below)...

>+  (and (match_code "const_vector")
>+       (match_test "mips_const_vector_same_byte_p (op, mode)")))

This is no different from mips_const_vector_same_val_p excep for a mode
assertion. This constraint may as well just verify that all elements are the
same value and I think we can reasonably expect that you can't construct
a V16QI vec_const with values outside of an 8-bit range. Perhaps call it
Uxvx to indicate it is just checking mode width. Obviously this cannot be
used in a context where an immediate is implicitly sign extended but that
is what the other constraints are for.
You can then delete mips_const_vector_same_byte_p.

>diff --git a/gcc/config/mips/mips-ftypes.def b/gcc/config/mips/mips-ftypes.def
>index d56accc..29ef33c 100644
>--- a/gcc/config/mips/mips-ftypes.def
>+++ b/gcc/config/mips/mips-ftypes.def
>@@ -36,6 +36,226 @@ along with GCC; see the file COPYING3.  If not see
> DEF_MIPS_FTYPE (1, (DF, DF))
> DEF_MIPS_FTYPE (2, (DF, DF, DF))
> 
>+DEF_MIPS_FTYPE (2, (V16QI, V16QI, V16QI))

...

Please sort these as the file requests towards the top. I have not checked
these are all needed but am assuming they are.

Thanks,
Matthew