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[PATCH][AArch64 array_mode 2/8] Remove VSTRUCT_DREG, use BLKmode for d-reg aarch64_st/ld expands
- From: Alan Lawrence <alan dot lawrence at arm dot com>
- To: gcc-patches at gcc dot gnu dot org
- Cc: james dot greenhalgh at arm dot com, marcus dot shawcroft at arm dot com
- Date: Wed, 26 Aug 2015 14:46:53 +0100
- Subject: [PATCH][AArch64 array_mode 2/8] Remove VSTRUCT_DREG, use BLKmode for d-reg aarch64_st/ld expands
- Authentication-results: sourceware.org; auth=none
- References: <1440596819-18018-1-git-send-email-alan dot lawrence at arm dot com>
aarch64_st<VSTRUCT:nregs><VDC:mode> and
aarch64_ld<VSTRUCT:nregs><VDC:mode> expanders back onto 12 insns
aarch64_{ld,st}{2,3,4}<mode>_dreg (for VD and DX modes), using the
VSTRUCT_DREG iterator over TI/EI/OI modes to represent the block of memory
transferred. Instead, use BLKmode for all memory transfers, explicitly setting
mem_size.
Bootstrapped and check-gcc on aarch64-none-linux-gnu.
gcc/ChangeLog:
* config/aarch64/aarch64-simd.md
(aarch64_ld2<mode>_dreg VD & DX, aarch64_st2<mode>_dreg VD & DX ):
Change all TImode operands to BLKmode.
(aarch64_ld3<mode>_dreg VD & DX, aarch64_st3<mode>_dreg VD & DX):
Change all EImode operands to BLKmode.
(aarch64_ld4<mode>_dreg VD & DX, aarch64_st4<mode>_dreg VD & DX):
Change all OImode operands to BLKmode.
(aarch64_ld<VSTRUCT:nregs><VDC:mode>,
aarch64_st<VSTRUCT:nregs><VDC:mode>): Generate MEM rtx with BLKmode
and call set_mem_size.
* config/aarch64/iterators.md (VSTRUCT_DREG): Remove.
---
gcc/config/aarch64/aarch64-simd.md | 44 +++++++++++++++++++-------------------
gcc/config/aarch64/iterators.md | 2 --
2 files changed, 22 insertions(+), 24 deletions(-)
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index 3796386..7b7a1b8 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -4393,7 +4393,7 @@
(subreg:OI
(vec_concat:<VRL2>
(vec_concat:<VDBL>
- (unspec:VD [(match_operand:TI 1 "aarch64_simd_struct_operand" "Utv")]
+ (unspec:VD [(match_operand:BLK 1 "aarch64_simd_struct_operand" "Utv")]
UNSPEC_LD2)
(vec_duplicate:VD (const_int 0)))
(vec_concat:<VDBL>
@@ -4410,7 +4410,7 @@
(subreg:OI
(vec_concat:<VRL2>
(vec_concat:<VDBL>
- (unspec:DX [(match_operand:TI 1 "aarch64_simd_struct_operand" "Utv")]
+ (unspec:DX [(match_operand:BLK 1 "aarch64_simd_struct_operand" "Utv")]
UNSPEC_LD2)
(const_int 0))
(vec_concat:<VDBL>
@@ -4428,7 +4428,7 @@
(vec_concat:<VRL3>
(vec_concat:<VRL2>
(vec_concat:<VDBL>
- (unspec:VD [(match_operand:EI 1 "aarch64_simd_struct_operand" "Utv")]
+ (unspec:VD [(match_operand:BLK 1 "aarch64_simd_struct_operand" "Utv")]
UNSPEC_LD3)
(vec_duplicate:VD (const_int 0)))
(vec_concat:<VDBL>
@@ -4450,7 +4450,7 @@
(vec_concat:<VRL3>
(vec_concat:<VRL2>
(vec_concat:<VDBL>
- (unspec:DX [(match_operand:EI 1 "aarch64_simd_struct_operand" "Utv")]
+ (unspec:DX [(match_operand:BLK 1 "aarch64_simd_struct_operand" "Utv")]
UNSPEC_LD3)
(const_int 0))
(vec_concat:<VDBL>
@@ -4472,7 +4472,7 @@
(vec_concat:<VRL4>
(vec_concat:<VRL2>
(vec_concat:<VDBL>
- (unspec:VD [(match_operand:OI 1 "aarch64_simd_struct_operand" "Utv")]
+ (unspec:VD [(match_operand:BLK 1 "aarch64_simd_struct_operand" "Utv")]
UNSPEC_LD4)
(vec_duplicate:VD (const_int 0)))
(vec_concat:<VDBL>
@@ -4499,7 +4499,7 @@
(vec_concat:<VRL4>
(vec_concat:<VRL2>
(vec_concat:<VDBL>
- (unspec:DX [(match_operand:OI 1 "aarch64_simd_struct_operand" "Utv")]
+ (unspec:DX [(match_operand:BLK 1 "aarch64_simd_struct_operand" "Utv")]
UNSPEC_LD4)
(const_int 0))
(vec_concat:<VDBL>
@@ -4526,8 +4526,8 @@
(unspec:VDC [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
"TARGET_SIMD"
{
- machine_mode mode = <VSTRUCT:VSTRUCT_DREG>mode;
- rtx mem = gen_rtx_MEM (mode, operands[1]);
+ rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
+ set_mem_size (mem, <VSTRUCT:nregs> * 8);
emit_insn (gen_aarch64_ld<VSTRUCT:nregs><VDC:mode>_dreg (operands[0], mem));
DONE;
@@ -4765,8 +4765,8 @@
)
(define_insn "aarch64_st2<mode>_dreg"
- [(set (match_operand:TI 0 "aarch64_simd_struct_operand" "=Utv")
- (unspec:TI [(match_operand:OI 1 "register_operand" "w")
+ [(set (match_operand:BLK 0 "aarch64_simd_struct_operand" "=Utv")
+ (unspec:BLK [(match_operand:OI 1 "register_operand" "w")
(unspec:VD [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
UNSPEC_ST2))]
"TARGET_SIMD"
@@ -4775,8 +4775,8 @@
)
(define_insn "aarch64_st2<mode>_dreg"
- [(set (match_operand:TI 0 "aarch64_simd_struct_operand" "=Utv")
- (unspec:TI [(match_operand:OI 1 "register_operand" "w")
+ [(set (match_operand:BLK 0 "aarch64_simd_struct_operand" "=Utv")
+ (unspec:BLK [(match_operand:OI 1 "register_operand" "w")
(unspec:DX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
UNSPEC_ST2))]
"TARGET_SIMD"
@@ -4785,8 +4785,8 @@
)
(define_insn "aarch64_st3<mode>_dreg"
- [(set (match_operand:EI 0 "aarch64_simd_struct_operand" "=Utv")
- (unspec:EI [(match_operand:CI 1 "register_operand" "w")
+ [(set (match_operand:BLK 0 "aarch64_simd_struct_operand" "=Utv")
+ (unspec:BLK [(match_operand:CI 1 "register_operand" "w")
(unspec:VD [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
UNSPEC_ST3))]
"TARGET_SIMD"
@@ -4795,8 +4795,8 @@
)
(define_insn "aarch64_st3<mode>_dreg"
- [(set (match_operand:EI 0 "aarch64_simd_struct_operand" "=Utv")
- (unspec:EI [(match_operand:CI 1 "register_operand" "w")
+ [(set (match_operand:BLK 0 "aarch64_simd_struct_operand" "=Utv")
+ (unspec:BLK [(match_operand:CI 1 "register_operand" "w")
(unspec:DX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
UNSPEC_ST3))]
"TARGET_SIMD"
@@ -4805,8 +4805,8 @@
)
(define_insn "aarch64_st4<mode>_dreg"
- [(set (match_operand:OI 0 "aarch64_simd_struct_operand" "=Utv")
- (unspec:OI [(match_operand:XI 1 "register_operand" "w")
+ [(set (match_operand:BLK 0 "aarch64_simd_struct_operand" "=Utv")
+ (unspec:BLK [(match_operand:XI 1 "register_operand" "w")
(unspec:VD [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
UNSPEC_ST4))]
"TARGET_SIMD"
@@ -4815,8 +4815,8 @@
)
(define_insn "aarch64_st4<mode>_dreg"
- [(set (match_operand:OI 0 "aarch64_simd_struct_operand" "=Utv")
- (unspec:OI [(match_operand:XI 1 "register_operand" "w")
+ [(set (match_operand:BLK 0 "aarch64_simd_struct_operand" "=Utv")
+ (unspec:BLK [(match_operand:XI 1 "register_operand" "w")
(unspec:DX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
UNSPEC_ST4))]
"TARGET_SIMD"
@@ -4830,8 +4830,8 @@
(unspec:VDC [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
"TARGET_SIMD"
{
- machine_mode mode = <VSTRUCT:VSTRUCT_DREG>mode;
- rtx mem = gen_rtx_MEM (mode, operands[0]);
+ rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
+ set_mem_size (mem, <VSTRUCT:nregs> * 8);
emit_insn (gen_aarch64_st<VSTRUCT:nregs><VDC:mode>_dreg (mem, operands[1]));
DONE;
diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md
index b19d3d7..98b6714 100644
--- a/gcc/config/aarch64/iterators.md
+++ b/gcc/config/aarch64/iterators.md
@@ -559,8 +559,6 @@
(V4SI "V16SI") (V4SF "V16SF")
(V2DI "V8DI") (V2DF "V8DF")])
-(define_mode_attr VSTRUCT_DREG [(OI "TI") (CI "EI") (XI "OI")])
-
;; Mode of pair of elements for each vector mode, to define transfer
;; size for structure lane/dup loads and stores.
(define_mode_attr V_TWO_ELEM [(V8QI "HI") (V16QI "HI")
--
1.8.3