Re: [PATCH], PowerPC IEEE 128-bit patch #5

[Michael Meissner <meissner at linux dot vnet dot ibm dot com>]

On Wed, Aug 19, 2015 at 07:41:24AM -0500, Segher Boessenkool wrote:
> On Fri, Aug 14, 2015 at 11:46:03AM -0400, Michael Meissner wrote:
> > +;; Like int_reg_operand, but don't return true for pseudo registers
> > +(define_predicate "int_reg_operand_not_pseudo"
> > +  (match_operand 0 "register_operand")
> > +{
> > +  if ((TARGET_E500_DOUBLE || TARGET_SPE) && invalid_e500_subreg (op, mode))
> > +    return 0;
> > +
> > +  if (GET_CODE (op) == SUBREG)
> > +    op = SUBREG_REG (op);
> > +
> > +  if (!REG_P (op))
> > +    return 0;
> > +
> > +  if (REGNO (op) >= FIRST_PSEUDO_REGISTER)
> > +    return 0;
> > +
> > +  return INT_REGNO_P (REGNO (op));
> > +})
> 
> Since you use this only once, maybe it is easier (to read, etc.) if you
> just test it there?  Hard regs do not get subregs.

I was worried about hard regs appearing before reload, and possibly being
subregs, so I'll remove the SUBREG test.

> > +(define_insn_and_split "ieee_128bit_vsx_neg<mode>2"
> > +  [(set (match_operand:TFIFKF 0 "register_operand" "=wa")
> > +	(neg:TFIFKF (match_operand:TFIFKF 1 "register_operand" "wa")))
> > +   (clobber (match_scratch:V16QI 2 "=v"))]
> > +  "TARGET_FLOAT128 && FLOAT128_IEEE_P (<MODE>mode)"
> > +  "#"
> > +  "&& 1"
> > +  [(parallel [(set (match_dup 0)
> > +		   (neg:TFIFKF (match_dup 1)))
> > +	      (use (match_dup 2))])]
> > +{
> > +  if (GET_CODE (operands[2]) == SCRATCH)
> > +    operands[2] = gen_reg_rtx (V16QImode);
> > +
> > +  operands[3] = gen_reg_rtx (V16QImode);
> > +  emit_insn (gen_ieee_128bit_negative_zero (operands[2]));
> > +}
> > +  [(set_attr "length" "8")
> > +   (set_attr "type" "vecsimple")])
> 
> Where is operands[3] used?  I guess that whole line should be deleted?

Good catch. It was from the earlier patch before the fix for PR 67071, which
added better support for vector constants that can be constructed with several
vector operations, including a vector octet shift.

> > +(define_insn "*ieee_128bit_vsx_neg<mode>2_internal"
> > +  [(set (match_operand:TFIFKF 0 "register_operand" "=wa")
> > +	(neg:TFIFKF (match_operand:TFIFKF 1 "register_operand" "wa")))
> > +   (use (match_operand:V16QI 2 "register_operand" "=v"))]
> > +  "TARGET_FLOAT128"
> > +  "xxlxor %x0,%x1,%x2"
> > +  [(set_attr "length" "4")
> > +   (set_attr "type" "vecsimple")])
> 
> Length 4 is default, you can just leave it out (like we do for most
> machine insns already).

Ok, though I tend to always put them in.

Here is the revised patch. Is it ok to install?

2015-08-25  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* config/rs6000/predicates.md (int_reg_operand_not_pseudo): New
	predicate for only GPR hard registers.

	* config/rs6000/rs6000.md (FP): Add IEEE 128-bit floating point
	modes to iterators. Add new iterators for moving 128-bit values in
	scalar FPR registers and VSX registers.
	(FMOVE128): Likewise.
	(FMOVE128_FPR): Likewise.
	(FMOVE128_GPR): Likewise.
	(FMOVE128_VSX): Likewise.
	(FLOAT128_SFDFTF): New iterators for IEEE 128-bit floating point
	in VSX registers.
	(IFKF): Likewise.
	(IBM128): Likewise.
	(TFIFKF): Likewise.
	(RELOAD): Add IEEE 128-bit floating point modes.
	(signbittf2): Convert TF insns to add support for new IEEE 128-bit
	floating point in VSX registers modes.
	(signbit<mode>2, IBM128 iterator): Likewise.
	(mov<mode>_64bit_dm, FMOVE128_FPR iterator): Likewise.
	(mov<mode>_32bit, FMOVE128_FPR iterator): Likewise.
	(negtf2): Likewise.
	(neg<mode>2, TFIFKF iterator): Likewise.
	(negtf2_internal): Likewise.
	(abstf2): Likewise.
	(abs<mode>2, TFIFKF iterator): Likewise.
	(ieee_128bit_negative_zero): New IEEE 128-bit floating point in
	VSX insn support for negate, absolute value, and negative absolute
	value.
	(ieee_128bit_vsx_neg<mode>2): Likewise.
	(ieee_128bit_vsx_neg<mode>2_internal): Likewise.
	(ieee_128bit_vsx_abs<mode>2): Likewise.
	(ieee_128bit_vsx_abs<mode>2_internal): Likewise.
	(ieee_128bit_vsx_nabs<mode>2): Likewise.
	(ieee_128bit_vsx_nabs<mode>2_internal): Likewise.
	(FP128_64): Update pack/unpack 128-bit insns for IEEE 128-bit
	floating point in VSX registers.
	(unpack<mode>_dm): Likewise.
	(unpack<mode>_nodm): Likewise.
	(pack<mode>): Likewise.
	(unpackv1ti): Likewise.
	(unpack<mode>, FMOVE128_VSX iterator): Likewise.
	(packv1ti): Likewise.
	(pack<mode>, FMOVE128_VSX iterator): Likewise.

-- 
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.vnet.ibm.com, phone: +1 (978) 899-4797

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