This is the mail archive of the gcc-patches@gcc.gnu.org mailing list for the GCC project.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

[PATCH] Improve performance for Haswell family.


Hi All,

Here is patch which contains
(1) modifying of core2.md  to conform Haswell pipeline and adding of
missed instruction reservation for instructions with vector operands.
(2) increase reassociation width for float-point operations for
Haswell family and 64-bit target, this allows to get +10% speedup on
spec2006/410.bwaves for Skylake processor.

Bootstrap and regression testing did not show any new failures.
Is it OK for trunk?

ChangeLog:
2015-08-14  Yuri Rumyantsev  <ysrumyan@gmail.com>

* config/i386/core2.md: Confrom instruction reservation to Haswell
pipeline.
* config/i386/i386.c (ix86_reassociation_width): Increase reassociation
width for float-point operations.

Attachment: hsw.patch
Description: Binary data


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]