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Re: [PATCH][AArch64] PR target/65491: Classify V1TF vectors as AAPCS64 short vectors rather than composite types

On Mon, Apr 20, 2015 at 11:16:02AM +0100, Kyrylo Tkachov wrote:
> Hi all,
> The ICE in the PR happens when we pass a 1x(128-bit float) vector as an
> argument.
> The aarch64 backend erroneously classifies it as a composite type when in
> fact it
> is a short vector according to AAPCS64
> (section 4.1.2 from
> df).


> The solution in this patch is to check aarch64_composite_type_p for a short
> vector with
> aarch64_short_vector_p rather than the other way around (check for
> aarch64_short_vector_p
> in aarch64_composite_type_p).

I think I understand what you are saying, but your patch does the
opposite (ADDS a check for aarch64_short_vector_p in
aarch64_composite_type_p, REMOVES a check for aarch64_composite_type_p,
in aarch64_short_vector_p)...

This logic is pretty hairy, and I'm struggling to convince myself that
your change only hits the bug you described above. I think I've worked
it through and it does, but if you can find any additional ABI tests
which stress the Vector/Floating-Point passing rules that would help
settle my nerves.

The patch is OK. I wouldn't think we would want to backport it to
release branches as there is no regression to fix.


> 2015-04-20  Kyrylo Tkachov  <>
>     PR target/65491
>     * config/aarch64/aarch64.c (aarch64_short_vector_p): Move above
>     aarch64_composite_type_p.  Remove check for aarch64_composite_type_p.
>     (aarch64_composite_type_p): Return false if given type and mode are
>     for a short vector.
> 2015-04-20  Kyrylo Tkachov  <>
>     PR target/65491
>     * New test.
>     * (vlf1_t): New typedef.
>     * Add test for vlf1_t.

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