No new code here ;). There is a slight change of execution path, i.e. some
VEC_PERM_EXPRs (e.g. those for reductions via shifts) will be expanded using
arm_expand_vec_perm_const rather than the vec_shr pattern. This generates EXT
instructions equivalent to the original, but using the mode of the source
vector, rather than always indexing in terms of 8-bit elements.
vec_shl in contrast was never used.
Cross-tested check-gcc on arm-none-eabi.
gcc/ChangeLog:
* config/arm/neon.md (vec_shl<mode>, vec_shr<mode>): Remove.
diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
index 41cf913a0da2e3ec034884ebb04bff9be7db3025..4297b0cd36a660bef5e2e66e2d5030c7cb6af2d3 100644
--- a/gcc/config/arm/neon.md
+++ b/gcc/config/arm/neon.md
@@ -1194,71 +1194,6 @@
[(set_attr "type" "neon_add_widen")]
)
-;; VEXT can be used to synthesize coarse whole-vector shifts with 8-bit
-;; shift-count granularity. That's good enough for the middle-end's current
-;; needs.
-
-;; Note that it's not safe to perform such an operation in big-endian mode,
-;; due to element-ordering issues.
-
-(define_expand "vec_shr_<mode>"
- [(match_operand:VDQ 0 "s_register_operand" "")
- (match_operand:VDQ 1 "s_register_operand" "")
- (match_operand:SI 2 "const_multiple_of_8_operand" "")]
- "TARGET_NEON && !BYTES_BIG_ENDIAN"
-{
- rtx zero_reg;
- HOST_WIDE_INT num_bits = INTVAL (operands[2]);
- const int width = GET_MODE_BITSIZE (<MODE>mode);
- const enum machine_mode bvecmode = (width == 128) ? V16QImode : V8QImode;
- rtx (*gen_ext) (rtx, rtx, rtx, rtx) =
- (width == 128) ? gen_neon_vextv16qi : gen_neon_vextv8qi;
-
- if (num_bits == width)
- {
- emit_move_insn (operands[0], operands[1]);
- DONE;
- }
-
- zero_reg = force_reg (bvecmode, CONST0_RTX (bvecmode));
- operands[0] = gen_lowpart (bvecmode, operands[0]);
- operands[1] = gen_lowpart (bvecmode, operands[1]);
-
- emit_insn (gen_ext (operands[0], operands[1], zero_reg,
- GEN_INT (num_bits / BITS_PER_UNIT)));
- DONE;
-})
-
-(define_expand "vec_shl_<mode>"
- [(match_operand:VDQ 0 "s_register_operand" "")
- (match_operand:VDQ 1 "s_register_operand" "")
- (match_operand:SI 2 "const_multiple_of_8_operand" "")]
- "TARGET_NEON && !BYTES_BIG_ENDIAN"
-{
- rtx zero_reg;
- HOST_WIDE_INT num_bits = INTVAL (operands[2]);
- const int width = GET_MODE_BITSIZE (<MODE>mode);
- const enum machine_mode bvecmode = (width == 128) ? V16QImode : V8QImode;
- rtx (*gen_ext) (rtx, rtx, rtx, rtx) =
- (width == 128) ? gen_neon_vextv16qi : gen_neon_vextv8qi;
-
- if (num_bits == 0)
- {
- emit_move_insn (operands[0], CONST0_RTX (<MODE>mode));
- DONE;
- }
-
- num_bits = width - num_bits;
-
- zero_reg = force_reg (bvecmode, CONST0_RTX (bvecmode));
- operands[0] = gen_lowpart (bvecmode, operands[0]);
- operands[1] = gen_lowpart (bvecmode, operands[1]);
-
- emit_insn (gen_ext (operands[0], zero_reg, operands[1],
- GEN_INT (num_bits / BITS_PER_UNIT)));
- DONE;
-})
-
;; Helpers for quad-word reduction operations
; Add (or smin, smax...) the low N/2 elements of the N-element vector