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Hello! As shown in the PR, the attached patch substantial improves generated code when cmpxchg}8,16}b insn is involved. Following testcase: --cut here-- __int128_t i; int main() { __atomic_store_16(&i, -1, 0); if (i != -1) __builtin_abort(); return 0; } --cut here-- compiles with -O2 -mcx16 to: movq i(%rip), %rax movq $-1, %rcx movq i+8(%rip), %rdx .L2: movq %rcx, %rbx lock cmpxchg16b i(%rip) jne .L2 where without the patch, the compiler generated: movq i(%rip), %rsi movq $-1, %rcx movq i+8(%rip), %rdi .L2: movq %rsi, %rax movq %rdi, %rdx movq %rcx, %rbx lock cmpxchg16b i(%rip) movq %rdx, %rdi movq %rax, %rsi jne .L2 2015-03-31 Uros Bizjak <ubizjak@gmail.com> PR target/58945 * config/i386/sync.md (atomic_compare_and_swap<dwi>_doubleword): Do not split operands 0 and operands 2 to halfmode. (atomic_compare_and_swap<mode>): Update for atomic_compare_and_swap<dwi>_doubleword changes. Patch was bootstrapped and regression tested on x86_64-linux-gnu {,-m32} and was committed to mainline. Uros.
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